May 2018 – May 2023 · 5 yrs · Bengaluru

• Led a charter of SoC & Sub-system RTL Front-End. Responsible for key products development for AI, Client, & Edge application.
• SoC Chip Lead: Handled a vertical role SoC end-to-end execution from spec to commercialization for Client, IoT (AI Server class) chip.
• SaturnLake, Thunder Bay: NPU & ARM based product with external 7nm foundry and production worthy first silicon for server-class high efficiency Video Inferencing & Transcoding accelerator.

Oct 2015 – May 2018 · 2 yrs 7 mos · Bengaluru

• Technology : Responsible for SoC execution for High-tier Snapdragon Machine Learning Mobile/Tablet SoCs SDM715 (w/ NPU), SDM660, SDM630 from spec to productization.
• Focused on SoC execution with multiple teams - Architecture, Performance, Design, Implementation, DFT, Timing Sign-off, Physical Design, Methodology, Verification, GLS, Emulation, Power & Performance, Packaging, Board, Software and Post-Si validation.
• Management : Work with resource managers for resource planning and securing milestone.
• Presents SoC execution weekly status to program and BU management.

May 2015 – Oct 2015 · 5 mos · Bengaluru, Karnataka, India

• Participated in MSM SoC execution in Hsinchu, Taiwan (HQ)

Feb 2013 – May 2015 · 2 yrs 3 mos · Greater Noida

• Owned Set-top-Box SoCs (02) Front-End Design: Micro-Arch, RTL Integration, Implementation, Infra Logic for all SoCs. Worked on development plan for team members and empower them for their career growth.
• Management : Resource planning, Project reviews, team management and work on ramp-up plan for skill development for team members.
• Presents SoC weekly status to upper management.

Jul 2010 – Jan 2013 · 2 yrs 6 mos · Greater Noida

• Managed all Front-End design activities for SoC for Set-top-Box and DVD application.
• Executed Front-End design and hand-off for DDR3 Sub-system and delivered for various SoC across the groups.

Jan 2006 – Feb 2009 · 3 yrs 1 mo · Greater Noida

• Managed SoC full chip level timing signoff team, executed and successfully delivered multiple SoCs for Set-Top-Box and DVD application.

Aug 2004 – Dec 2005 · 1 yr 4 mos · Noida Area, India

• Display sub-system design and implementation for Set-Top-Box and DVD SoCs.
• Work with Architect to create micro-architecture for Sub picture decoder, Inter-field processor, Blitter IPs and develop the RTL inline with the specification.
• Sub-system integration, constraint generation, equivalence check, test strategy implementation and collaborate with physical design team for design support and functional & timing ECO implementation.
• Perform pre & post layout timing analysis to meet the desired frequency.

Jun 2002 – Jul 2004 · 2 yrs 1 mo · Noida Area, India

• ST proprietary CPU Based sub-systems design, implementation and verification to SoC for Set-Top-Box and DVD application.
• Work with Architect to create micro-architecture for various cache memory architecture and develop the RTL inline with the specification.
• Sub-system integration, constraint generation, equivalence check, test strategy implementation.
• Develop verification strategy, new test cases and deliver fully verified sub-system.
• Perform pre & post layout timing analysis to meet the desired frequency.

Apr 2000 – May 2002 · 2 yrs 1 mo · Noida

• Pentium based CPU's blocks implementation.
• Manual synthesis, clock gating implementation, Equivalence check, test vector generation.
• Transistor level timing analysis.