Ravi Teja — Software Engineer

• Ravi is SoC Engineering Lead specialising on Leadership of Pre & Post Silicon Validation • Ravi excels in fostering innovation, leading team, taking complex technical SoC challenges and delivering flawless SoCs aligning to organizational objectives • Ravi is a specialist in SoC Functional Validation, skilled in both Pre-Silicon Emulation & Post-Silicon Validation. He has also contributed in SoC Functional Design Verification using RTL Simulation. With functional domain expertise in SoC DV, Emulation & Post-Si Validation, Ravi is well-equipped to handle end to end Verification & Validation of SoC Functional Correctness starting from RTL Simulation, progressing through Emulation & culminating in Post-Silicon Validation • Ravi has debugged 70+ RTL Design Issues. He authored over nine research papers & posters. He has received the Best Poster award twice at prestigious annual industry conferences, published one paper in a USA-based journal & another in a Hong Kong international journal, presented one paper at an IEEE conference & made three submissions to Q-Buzz & one to ARM GEC Ravi's past experience :- • CPU Subsystem (Compute): ARM A-Class Core, ARM R-Class Core,ARM M-Class Core,Synopsys ARC HS Core & RISC-V AX45, IBEX Cores • Functional Safety Island Subsystem (FuSa): Subsystem for Automotive Functional Safety L2/L3 ADAS/IVI • System Management Subsystem: SoC Boot, Security and Power Management Subsystem • Signal Processing Subsystem (SPT): Subsystem for Automotive ADAS L2/L3 Radar Compute Signal Processing • SoC Interrupt Controllers: GIC/NVIC/PLIC/ARC (ARM, RISC-V, Synopsys ARC architectures), Cross Triggering Engine • Memory Management IP's: CPU Memory Management Unit (MMU), Memory Protection Unit (MPU), Address Translation Unit (ATU) • Memory Controllers: NOR Flash Memory Controller & SRAM Memory Controller • LSIO Communication Protocols: Quad-SPI, I2C, MHU, UART • ARM Coresight Debug & Trace Modules: JTAG, ETM Trace, STM Trace, QDSS, ELA-600, ETR, ETF • SoC Automotive Clock Monitoring Unit & Voltage Monitoring Unit • Subsystem Clocking: PLL, Clock Dividers & Root Clock Generators • SoC DV Testbench Development & SoC Bring-up • Digital Functional & Analog PVT Testing Ravi is proficient in following Programming Languages: • C & Embedded C • Verilog • Assembly • Matlab • Python Emulators & simulator • Zebu, Palladium and Veloce emulators • RUMI Qualcomm • Questa Sim • Ravi completed his B-Tech from Delhi Technological University (Delhi College of Engineering), one of India’s top engineering College. He ranked in top 5% among 400 Electronics students

Stackforce AI infers this person is a SoC Validation Engineer with expertise in automotive and semiconductor industries.

Location: Bengaluru, Karnataka, India

Experience: 9 yrs 7 mos