P

Pothireddy Vishnu Vardhan Reddy

Software Engineer

Bengaluru, Karnataka, India14 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in ASIC and SoC design verification.
  • Proficient in SystemVerilog and UVM methodologies.
  • Strong background in RTL design and functional verification.
Stackforce AI infers this person is a VLSI design verification expert with a focus on ASIC and SoC technologies.

Contact

Skills

Core Skills

AsicFunctional Verification

Other Skills

System VerilogVerilogUVMFunctional CoverageMemory VIPSBus protocol componentsSoC Design & Verification Life CyclesCC++Object Oriented MethodologyModelSimVLSIRTL designRTL codingLogic Design

About

To acquire a pre-eminent position in the corporate world as a respected professional through intrinsic value addition by working for a leading corporate that offers a creative learning opportunity.

Experience

14 yrs 6 mos
Total Experience
6 yrs 9 mos
Average Tenure
1 yr
Current Experience

Arm

SoC Design verification Engineer

Apr 2025Present · 1 yr · India · Hybrid

Mediatek

3 roles

Sr Staff Engineer

Jun 2019Mar 2025 · 5 yrs 9 mos

Staff Engineer

Promoted

Jun 2015May 2019 · 3 yrs 11 mos

Sr Verification Engineer

Aug 2014May 2015 · 9 mos

Whizchip design technologies pvt ltd

ASIC Verification Engineer

Jul 2011Aug 2014 · 3 yrs 1 mo · Bangalore

  • Hands on Experience in System Verilog, Verilog
  • Good Knowledge and hands on experience of UVM/OVM/VMM.
  • Well versed in creating the UVC’s, OVC's
  • Good Knowledge and hands on experience of Functional Coverage.
  • Good Knowledge and hands on experience in Developing Memory VIPS and Bus protocol components.
  • Familiar with protocols like DDR4, D-PHY3.0, GDDR5, AMBA4.0, AMBA CHI .
  • Good understanding of Verification flow at SoC level and at IP level
  • Good Knowledge of ASIC & SoC Design & Verification Life Cycles.
  • Good knowledge of concepts in C,C++ and Object Oriented Methodology
  • Have good communication skills, interpersonal relations, analytical skills, hardworking and result oriented as an individual and in a team.
  • Willing to learn new skills and ability to learn fast.
System VerilogVerilogUVMFunctional CoverageMemory VIPSBus protocol components+6

Education

Manipal Center for Information Sciences

M.S — VLSI

Jan 2010Jan 2012

Narayana Engg College

Bachelor of Technology (B.Tech.) — Electronics Engineering(Specalisation in Biomedical)

Jan 2003Jan 2007

Narayana Junior College

Senior Secondary School

Jan 2001Jan 2003

Sri Netaji Pilot High School

High School

Jan 1989Jan 2001

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