Saurabh Sinha

CTO

Austin, Texas, United States18 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in Design Technology Co-optimization for advanced nodes.
Strong background in predictive modeling and semiconductor technologies.
Ph.D. in Electrical and Electronics Engineering from Arizona State University.

Stackforce AI infers this person is a Semiconductor Research Engineer with expertise in advanced technology nodes and predictive modeling.

Contact

Skills

Core Skills

SemiconductorsVlsiDesign Technology Co-optimizationResearchPredictive Technology ModelingPredictive Technology Models

Other Skills

VerilogMatlabCC++BSIM ProPlusHSPICESPICEMicroprocessorsVHDLASICPerlCircuit DesignSimulationsCadence VirtuosoCMOS

About

Experienced engineer with a demonstrated history of working in the semiconductors industry. Research interests include design-technology co-optimization at advanced technology nodes, predictive modeling of transistors and interconnects, physical design and benchmarking of disruptive technologies such as 3D integration. Strong engineering professional with a Doctor of Philosophy (Ph.D.) focused in Electrical and Electronics Engineering from Arizona State University.

Experience

18 yrs 8 mos

Total Experience

6 yrs 8 mos

Average Tenure

5 yrs 3 mos

Current Experience

Apple

Technology Pathfinding Engineer

Jan 2021 – Present · 5 yrs 3 mos · Austin, Texas, United States

VerilogMatlabCC++BSIM ProPlusHSPICE+24

Arm

4 roles

Principal Research Engineer

Promoted

Apr 2019 – Jan 2021 · 1 yr 9 mos

EE researcher with interest in Design Technology Co-optimization (DTCO) for advanced technologies, predictive modeling, 2.5D/3D technologies, 3D-IC design research, heterogeneous integration, photonics and plasmonics as drivers for next generation computing platforms.

Design Technology Co-optimizationpredictive modeling2.5D/3D technologies3D-IC design researchheterogeneous integrationphotonics+2

Staff Research Engineer

Jan 2015 – Apr 2019 · 4 yrs 3 mos

Predictive Technology modeling and Predictive PDK including FinFET transistor models, design rule checks, parasitic extraction and benchmarking for advanced nodes. Design Technology Co-optimization for advanced technology nodes such as 14nm, 10nm, 7nm and more. Evaluating transistor technologies (FinFETs, high mobility devices, gate-all-around structures, etc.) for advanced nodes. Early engagement with foundry partners, guiding design teams on potentially disrupting technology choices such as 3DIC.

Predictive Technology modelingPredictive PDKFinFET transistor modelsdesign rule checksparasitic extractionbenchmarking+5

Senior Design Engineer

Nov 2011 – Dec 2014 · 3 yrs 1 mo

Development of Predictive Technology Models for FinFETs. Understand impact on power-performance for future microprocessors. Identify, characterize and analyze impact of variation in future technology nodes. Early engagement with foundries for device-technology co-optimization, guide design teams regarding new technologies and reduce time-to-market for partners.

Predictive Technology Modelspower-performance analysisvariation impact analysisdevice-technology co-optimizationDesign Technology Co-optimization

R&D Intern

May 2011 – Oct 2011 · 5 mos

Developing PTM (Predictive Technology Model) model files for 2012-2020 and run benchmark simulations to understand performance impact and trade-offs involved with device scaling.

Predictive Technology Modelbenchmark simulations

Arizona state university

2 roles

Graduate Teaching Assistant

Jan 2011 – May 2011 · 4 mos

Worked as a Lab TA for EEE 525 VLSI Design course homeworks and projects.

Graduate Research Assistant

May 2007 – Dec 2010 · 3 yrs 7 mos

Research on scaling on-chip spiral inductors with integrated magnetic materials. Understand the impact of magnetic materials and structural optimization on inductance gain, frequency response and performance of inductors. Explored potential applications for magnetic inductors such as resonant clock distribution and on-chip dc-dc power converters. Explored the utilization of these inductors for per-core fast-transitioning dynamic voltage and frequency scaling in microprocessors.