Apr 2025 – Dec 2025 · 8 mos

Oct 2017 – Present · 8 yrs 6 mos · Greater San Diego Area · On-site

• Lead engineering and manufacturing operations for 4 system level products with various certifications, including ISO, IEC, JDEC, and ITAR.
• Collaborated with Azure IoT teams to lead the Ectron's team in the development of the SmartEYE Hybrid edge plus cloud IoT platform in 2018/2019.
• Established partnerships with key companies like Microsoft, Arrow Electronics, Intel, and Xilinx/AMD.
• Architected and led development of Ectron's rugged, AI/ML capable edge computers in 2018/2019
• Manage the US and India based hardware, software and systems team along with manufacturing and testing.
• Have also worked on various defense related projects over my career, some of these systems are widely deployed. The engineering team I manage other than doing re-engineering of Ectron products also provides solutions for customers in industrial, aerospace and defense markets for comms (SDR), networking, controls and other embedded and systems level applications/solutions.
• 1 patent issued and more in the pipeline

Apr 2016 – Oct 2017 · 1 yr 6 mos · Greater San Diego Area

• Developed a new processor architecture and instruction set for AI/ML and DSP, demonstrated in FPGA with a cross compiler and auto-generation tool to accelerate 32-bit ARM code.
• Raised seed funding and led development of the MVP, led the strategy and direction of the company, resulting in 1 patent issued with a 2013 priority date.
• Founded Xceler Systems Inc. to develop "graph based," processing concepts that I developed during my MSEE in 2005 based on atomic instructions.
• Today's CGRA architectures are very similar and coarse-grained versions of prototypes developed by us at Xceler and demonstrated in 2014, 2015
• A lot of AI compilers today using the "Graph Approach," to breakdown tasks are similar to the cross compiler we developed for ARM code to port onto our non-Von Neuman architecture. Used ML techniques to determine optimal accelerator configuration for a set of problems.
• The architecture with closely coupled memory blocks to compute elements preceded the "in-memory," compute movement as well by at least 5 years.
• I did simulations, wrote the scheduler code and did the basic fine grained processor design with "Atomic," operations in 2005 during my MSEE coursework at UT Dallas. We were able to implement this in 2013-2014 due to better tools. Now with Openroad tools it might be easier to build an ASIC!!.
• 1 Patent issued with a 2013 priority date

Sep 2012 – Apr 2016 · 3 yrs 7 mos

• Advised companies on Business development, Manufacturing, and Technology Strategy.
• Conducted IP and Technology acquisition due diligence.
• Performed infringement due diligence for patent licensing strategy and portfolio optimization.
• Full time single father to my two young children

Feb 2012 – Sep 2012 · 7 mos · Mountain View

Jan 2007 – Oct 2011 · 4 yrs 9 mos

• Formerly Manovega Inc., helped sell the prototyping business to Polaris Design systems (www.polaris-ds.com) The CTO and I worked to get design wins at marquee customers such as Panasonic, Sharp, Mitsubishi and others. Setup partnerships with Texas Instruments, Altera and Mathworks. Ran operations, setup processes and managed a cross functional team. I also architected multi-FPGA, FPGA+DSP cards for heterogeneous computing and tried to spin off ACELER. Aceler's System Architecture is evident in the NVIDIA DGX-1 and today's data center accelerators using FPGAs. Oversaw, testing, design, manufacturing of the cards, integration of systems. The boards had a 256 Gbps interconnect between them and a control plane interconnect on PCIe to the host.
• We demoed MATLAB/Simulink being accelerated (HIL) on a remote server with FPGA offload at DAC with IPMI and remote management. Servers with FPGA accelerators in cloud data centers to offload workloads in use today!!

Aug 2004 – Feb 2006 · 1 yr 6 mos

• Managed a team delivering high speed serdes based applications and participated in other roles as required in technology, strategy and business development.
• Worked with strategic marketing and sales to push the applications team to align with the bottom line of the company in developing/working on projects that were customer oriented.
• 5 issued patents covering a novel "stream manager," and shared memory switch fabric design

Sep 2000 – Jul 2004 · 3 yrs 10 mos

• Founding CTO and VP of engineering of the company. Raised seed financing for the company, recruited the management, advisory board of industry veterans and helped start the India office for the company and engineering team in India predicting the transition of markets and design work to that country in 2000. Built the India team from scratch recruiting core team. Managed cross functional team to develop solutions in various verticals and customers. Worked with various local government and federal agencies for permits, licensing, business development: Export/Import, STPI (Software Technology Parks Initiative), Customs, Central Government labs and ministries.
• Set up processes for product development/release for smaller team based on INCOSE/MIL CMM standards, 360 reviews, KPI tracking, Product and Program management, cross geography governance, quality and testing (Document, version control etc). Team was assessed at CMM level 3 for a start up by Motorola India, Kirloskar Electric (www.kirloskar.com), BHEL (www.bhel.com) and various other agencies during Audits.
• Our young team built and demonstrated a Virtual Software Router in 2002. The design worked fully in software with real traffic or with hardware in loop such as FPGA cards plugged into a machine. We built multi-core processors in FPGA (NIOS) for our packet processing engines and schedulers. The multi-threaded machine associated a thread for each function in the pipeline from a parent system controller, where the child threads could write "data structures," or packets into R/W memory visible to the hardware negating the need for drivers. These virtual message queues were then managed by local schedulers, status updates were shared to a global scoreboard...each queue had its own property. Router could be in one box or multiple boxes.
• Proud of our team: Light years ahead (Today's NFV, Google Queues, graph processing)
• 4 issued patents
• Trade publication articles and IEEE conference papers

May 1999 – Jul 2000 · 1 yr 2 mos

• My team at Nortel provided presales support for HFC last mile network sales and in some cases for DSL and switching solutions. Worked with Nortel executives and Nortel JV Arris and ANTEC executives to push joint solutions in the HFC space. Customer successes included AT&T/TCI cable, Adelphia, Grande Communications. Work mainly involved:
• Business Cases for vendor/bank financing for greenfield deployments
• Network Planning, Traffic Analysis
• Pricing Analysis for services (bundled, unbundled)
• Product and new service Positioning
• Product feedback to systems engineering
• Received Two Nortel's presidents awards for excellent performance on customer engagements

Oct 1997 – Mar 1999 · 1 yr 5 mos

• Raised seed funding and evangelized the idea for packet computing (packet interconnects in a PC system). Patent for "Computer Having Packet Based Interconnect Channel," USPTO # 6009488 in 1997 that pre-dates PCI Express and Hyper Transport cited in over 500 issued patents related to QPI, PCI Express, USB 3.0 and other high speed packet interconnects. Developed proof of concept implementation for simulation and demonstration purposes.
• Some of the concepts have been moved inside chips to implement multi-core processors. Concepts introduced in the patent are used in almost every PC, Server, Microprocessor, Disks/Storage systems and packet based interconnects in the same.