Anantha Padmanabhan B M — Product Engineer
Digital ASIC design professional with end-to-end expertise in the RTL-to-GDSII flow, from specification through signoff, using the Cadence suite [Xcelium, Genus, Innovus, Conformal LEC, Tempus, Virtuoso] Skilled in physical design, static timing analysis (STA), and PPA optimization, with a strong track record of delivering timing-closed, power-efficient, and area-optimized designs at advanced nodes. Passionate about tackling complex design challenges and driving successful tapeouts. Ready to contribute to next-generation semiconductor development and help organizations achieve aggressive PPA and time-to-market goals.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC design and fabrication.
Location: Thiruvananthapuram, Kerala, India
Experience: 2 yrs 6 mos
Skills
- Semiconductor Fabrication
Career Highlights
- Expertise in RTL-to-GDSII flow and physical design.
- Proven track record in timing-closed, power-efficient designs.
- Passionate about complex design challenges and successful tapeouts.
Work Experience
Qualcomm
Physical Design Intern (3 mos)
Indian Institute of Information Technology (IIIT), Allahabad
Teaching Assistant (1 yr 5 mos)
Indian Institute of Science Education and Research, Thiruvananthapuram
Major Project (1 yr 1 mo)
Education
Master of Technology - MTech at Indian Institute of Information Technology (IIIT), Allahabad
BSMS at Indian Institute of Science Education and Research, Thiruvananthapuram
School at Christ Nagar School
