Tamal Das

Director of Engineering

Bengaluru, Karnataka, India18 yrs 6 mos experience
Highly StableAI Enabled

Key Highlights

  • 15+ years in analog/mixed-signal design.
  • Led 50+ SerDes test vehicle validations.
  • Expert in post-silicon debug and cross-functional execution.
Stackforce AI infers this person is a Semiconductor Design Expert specializing in Analog and Mixed Signal technologies.

Contact

Skills

Core Skills

LeadershipAnalog And Mixed Signal DesignAi Data CenterSerdesHardware Engineering

Other Skills

Silicon PhotonicsSystemVerilogProblem SolvingTeam BuildingTiming ClosureIP developmentCommunicationCustomer RequirementsDigital DesignsTeam ManagementAnalog VLSI DesignCPerlVerilogVerilog-A

About

My career has been a steady reminder that complex silicon keeps you humble—because the moment you start feeling confident, reality shows up with a brand-new failure mode and a deadline. By trade, I’m an analog/mixed-signal design leader with 15+ years building and validating 50+ SerDes test vehicles, delivering IP across storage, display, and networking—up to 224Gbps. I’ve spent a lot of time in post-silicon debug, customer escalations, and cross-functional global execution—where the real learning happens. I’ve learned that leadership isn’t about having all the answers—it’s about creating clarity when nobody does. I focus on teams that execute under uncertainty: crisp ownership, tight learning loops, honest risk burn-down, and calm escalation when things inevitably break. I started at Cosmic Circuits (later acquired by Cadence), where I learned strong fundamentals and the joy of building things that should work. At Samsung, I learned what “production reality” really means. I used to believe bench validation was the biggest proof—until I learned ATE matters even more for manufacturing. When ATE goes sideways, it’s a different kind of nightmare: limited analog visibility, fewer knobs, harder debug. And silicon validation teaches you something very specific: all the different ways things can go wrong. Somewhere in that environment, I learned how to sleep under immense pressure… and eventually how to thrive in it. Over the last two years, through multiple concurrent transitions, I’ve internalized a broader rule: whatever can go wrong, will go wrong—especially in roadmaps, dependencies, and org execution. So I plan for resilience: clearer ownership, earlier risk burn-down, fewer late surprises. Now at Krutrim, I work on high-speed interconnect / SerDes and increasingly AI datacenter connectivity, where silicon, package, test, and system constraints all collide in the real world.

Experience

18 yrs 6 mos
Total Experience
3 yrs 8 mos
Average Tenure
2 mos
Current Experience

Intel corporation

Director of Engineering

Feb 2026Present · 2 mos · Bengaluru, Karnataka, India · On-site

SerDesLeadershipAnalog and Mixed Signal Design

Krutrim

Director

Dec 2024Feb 2026 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

AI Data CenterSilicon PhotonicsAnalog and Mixed Signal Design

Samsung foundry

3 roles

Director of Engineering

Promoted

Feb 2023Sep 2024 · 1 yr 7 mos

SystemVerilogProblem SolvingSerDesHardware EngineeringTeam BuildingTiming Closure+4

Associate Director

Mar 2020Feb 2023 · 2 yrs 11 mos

SystemVerilogProblem SolvingSerDesHardware EngineeringTeam BuildingTiming Closure+5

Senior Staff Engineer

Apr 2017Mar 2020 · 2 yrs 11 mos

SystemVerilogProblem SolvingSerDesHardware EngineeringTiming ClosureIP development+2

Cadence design systems

3 roles

Principal Design Engineer

Aug 2016Apr 2017 · 8 mos

SystemVerilogProblem SolvingSerDesHardware EngineeringTiming ClosureIP development+4

Design Engineering Manager

Promoted

Jul 2015Aug 2016 · 1 yr 1 mo

SystemVerilogProblem SolvingSerDesHardware EngineeringTiming ClosureIP development+2

Lead Design Engineer

May 2013Jun 2015 · 2 yrs 1 mo

  • > Analog lead for high speed SerDes project.
  • > High Speed Transmitter design for multi-protocol SerDes IP. It includes PCIE3.0, USB3, DP, eDP, HDMI, SATA, standards in 16nm, 28nm process node.
  • > Expertized in high speed serializer (10Ghz)
SystemVerilogProblem SolvingSerDesHardware EngineeringTiming ClosureIP development+1

Cosmic circuits pvt. ltd.

2 roles

Design Engineer in Interface/Connectivity IP Group

Mar 2011May 2013 · 2 yrs 2 mos

  • > High Speed Transmitter design for Connectivity IP of MIPI M-PHY standards in 40nm, 28nm process node.
  • > Low Power/Speed RX/TX design for Connectivity IP of MIPI-D-PHY and M-PHY standards in 85nm, 65nm and 28nm process node
  • > AMS verification of Full TOP TX and RX of Connectivity IP in MIPI-D-PHY and M-PHY standards in 85nm, 65nm and 28nm process node
  • > Low power, low area Band-gap with strict PSRR spec. as common block of interface IP
SystemVerilogProblem SolvingSerDesHardware EngineeringTiming Closure

Design Engineer in ASIC Group

Jun 2010Mar 2012 · 1 yr 9 mos

  • > Low Power Band-Gap Design with strict PSRR and NOISE performance for touch screen sensor back-end AASIC (<20uA)
  • > Ultra Low Power Band-Gap Design big supply range (<5uA)
  • > Functional Verification of DIGITAL FILTER (SINC-Decimation and FIR Filters)
  • > Full top automated functional verification of touch screen sensor back-end
SystemVerilogProblem SolvingHardware Engineering

Advanced vlsi design lab

Research Consultant (Power Managment Group)

Jun 2007Jun 2010 · 3 yrs

  • Has proposed a low ripple high efficiency fully on-chip DC-DC Boost converter and has implemented the same in Si. Also proposed different linear and non-linear control techniques with Si proof.
  • Working on Analog VLSI Design in 0.18uM Epi-CMOS Process
  • Administer the analog design flow for 0.18uM process of Natioanl Semiconductor for Advanced VLSI Design
Hardware Engineering

Education

Indian Institute of Technology, Kharagpur

MS(R) — Micro-Electronics and VLSI

Jan 2007Jan 2010

Kalyani Govt. Engg. College, West Bengal University of Technology

BTECH — Electronics & Communication Engg.

Jan 2003Jan 2007

Kanchrapara Harnett High School

HS (10+2) — Sceince

Jan 2001Jan 2003

Kanchrapara Harnett High School

Madhyamik

Jan 1995Jan 2001

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