Vishesh Kumar

Software Engineer

Bengaluru, Karnataka, India2 yrs 10 mos experience
Most Likely To Switch

Key Highlights

  • Senior Engineer with expertise in RTL Design.
  • M.Tech in VLSI Design from NIT Hamirpur.
  • Strong foundation in VLSI and digital electronics.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on semiconductor technology.

Contact

vishesh17899@gmail.comLinkedIn

Skills

Other Skills

VerilogStatic Timing AnalysisPhysical DesignCircuitSchematic EditorLayout DesignElectronic CircuitsCircuit TheoryVery-Large-Scale Integration (VLSI)CMOSApplication-Specific Integrated Circuits (ASIC)Computer-Aided Design (CAD)Digital Electronics

Experience

2 yrs 10 mos
Total Experience
1 yr 5 mos
Average Tenure
1 yr 9 mos
Current Experience

Mediatek

2 roles

Senior Engineer

Jul 2024 – Present · 1 yr 9 mos

RTL Design

Jul 2023 – Jul 2024 · 1 yr

Training and placement cell, nit hamirpur

Training and Placement Representative

Jan 2023 – Jun 2024 · 1 yr 5 mos · Hamirpur, Himachal Pradesh, India

National institute of technology hamirpur

Graduate Teaching Assistant

Jan 2023 – Jun 2023 · 5 mos · Hamirpur, Himachal Pradesh, India · On-site

Capgemini

Analyst

Jun 2021 – Jul 2022 · 1 yr 1 mo

Highradius

Consultant

Apr 2020 – Jun 2020 · 2 mos · Bhubaneshwar, Orissa, India

Bharat electronics limited

Summer Intern

May 2019 – May 2019 · 0 mo · Ghaziabad, Uttar Pradesh, India

Education

National Institute of Technology Hamirpur

Master of Technology - MTech — VLSI Design

Aug 2022 – May 2024

Kalinga Institute of Industrial Technology, Bhubaneswar

Bachelor of Technology - BTech — Electronics and Telecommunication Engineering

Jul 2017 – May 2021

D.A.V. Public School

Higher Secondary — High School/Secondary Certificate Programs

Jun 2015 – Apr 2017

DAV Public School Kolkata

Secondary School

Apr 2015 – Present

Stackforce found 100+ more professionals with Verilog & Static Timing Analysis

Explore similar profiles based on matching skills and experience

Nikhil Singh

Nikhil Singh

Silicon Design Engineer 2

at AMD

Itarsi, India3 yrs 8 mos exp
SystemVerilogUniversal Verification Methodology (UVM)
Himanshu Gupta

Himanshu Gupta

Digital Design Engineer

at Intel Corporation

Lucknow, India1 yr 9 mos exp
Digital Circuit DesignVLSI
Dimple Lalwani

Dimple Lalwani

ASIC Design Engineer

at Meta

Bengaluru, India18 yrs 5 mos exp
SoCASIC
DU

Dheeraj Upadhyay

Lead Product Engineer

at Cadence

Noida, India4 yrs exp
Power AnalysisEM IR
Rashmi Soni

Rashmi Soni

Staff Engineer, Application Engineering

at Synopsys Inc

Bengaluru, India11 yrs 10 mos exp
Physical DesignVLSI
Shivam Singh

Shivam Singh

Staff Engineer

at MediaTek

Bengaluru, India5 yrs 7 mos exp
Srikanth Puvvada

Srikanth Puvvada

Senior Architect

at Krutrim

Bengaluru, India25 yrs 2 mos exp
Himanshu Sharma

Himanshu Sharma

Senior Engineer

at Qualcomm

Delhi, India6 yrs 8 mos exp
AMBA PROTOCOLSIP development