J Aarthi

Software Engineer

India8 yrs 9 mos experience
Highly Stable

Key Highlights

  • 4+ years in SoC and IP design for low power.
  • Expertise in boot bringup and power management IP.
  • Proven track record in RTL implementation and debugging.
Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on Low-power SoC architecture.

Contact

Skills

Core Skills

Soc DesignLow-power Design

Other Skills

Very-Large-Scale Integration (VLSI)System on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)DebugPower ManagementBoot Bringup IPRTL CodingSERDESStatic Timing AnalysisLogic SynthesisLogic Equivalence CheckLintCDCDFTGPIO

About

4+ years of experience in SoC and IP design for complex SoCs aimed at low power. Have experience in designing Boot Bringup IP, low power management IP FSMs, General Purpose IO controllers etc and Front End design flows.

Experience

8 yrs 9 mos
Total Experience
4 yrs 11 mos
Average Tenure
3 yrs 10 mos
Current Experience

Nvidia

Senior ASIC Engineer

Jun 2022Present · 3 yrs 10 mos

Very-Large-Scale Integration (VLSI)System on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)Low-power DesignDebugSoC Design

Samsung semiconductor india

4 roles

Staff Engineer

Mar 2022Jun 2022 · 3 mos

Associate Staff Engineer

Promoted

Mar 2020Mar 2022 · 2 yrs

  • ● Led the hierarchical power management architecture RTL implementation for the tape-out version of the test and the production chip of an AR/VR co-processor.
  • ● Implemented power management units for establishing multiple power domains in each submodule to support idle low power states.
  • ● Designed the boot sequencer module to support multiple boot modes.
  • ● Issued the sequence and debugged all the issues pertaining to bring up, power state transitions and power scenarios in RTL, GLS and post Silicon stages.
  • ● Designed the Process, Voltage, Temperature (PVT) Analog IP controller for managing the thermal conditions of the chip.
Power ManagementBoot Bringup IPRTL CodingDebugLow-power DesignSoC Design

Senior Hardware Engineer

Promoted

Mar 2018Mar 2020 · 2 yrs

Hardware Engineer

Jul 2017Mar 2018 · 8 mos

Education

National Institute of Technology, Tiruchirappalli

Bachelor of Technology (B.Tech Honors) — Electronics and Communications Engineering

Jan 2013Jan 2017

Kendriya Vidyalaya

Jan 2008Jan 2013

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