Chandramohan P

Software Engineer

India18 yrs 8 mos experience

Highly Stable

Key Highlights

16+ years in ASIC design and verification.
Expert in both Analog and Digital design flows.
Led multiple training programs for semiconductor engineers.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in ASIC and VLSI.

Contact

Skills

Core Skills

Physical DesignAsic SynthesisAsic Physical DesignAnalog Circuit Design

Other Skills

LECSTAPVIR dropDigital Circuit DesignMixed Signal Circuit DesignStandards Cell Library DevelopmentMemory DesignStatic Timing AnalysisIntegrated Circuit DesignVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)System on a Chip (SoC)

About

A dynamic, self motivated, committed, result oriented semiconductor professional with 16+ Years of experience in both Analog and Digital ASIC design flow Easily adopt to dynamic changes/environment on learning process, technology, flow, methodologies and best practices Experience in Synthesis, LEC, Physical Design, Physical Verification, STA and IR drop analysis for blocks/IPs/subsystems/SoCs using both Synopsys and Cadence EDA tools

Experience

18 yrs 8 mos

Total Experience

4 yrs 11 mos

Average Tenure

3 yrs 11 mos

Current Experience

Synopsys inc

2 roles

ASIC Physical Design, Staff Engineer

Promoted

Feb 2024 – Present · 2 yrs 4 mos

ASIC Physical Design Engineer Sr-1

Jun 2022 – Jan 2024 · 1 yr 7 mos

Mirafra technologies

3 roles

Principal Engineer

Promoted

Apr 2020 – Jun 2022 · 2 yrs 2 mos · Bengaluru, Karnataka, India

ASIC Synthesis, LEC, Physical Design, STA, PV and IR drop
Leading PD team

ASIC SynthesisLECPhysical DesignSTAPVIR drop

Senior Staff Engineer

Apr 2018 – Mar 2020 · 1 yr 11 mos · Bengaluru, Karnataka, India

ASIC Synthesis, LEC, Physical Design, STA, PV and IR drop

ASIC SynthesisLECPhysical DesignSTAPVIR drop

Staff Engineer

Apr 2017 – Mar 2018 · 11 mos · Bengaluru, Karnataka, India

ASIC Synthesis, LEC, Physical Design, STA, PV and IR drop
Lateral training programs for Hardware Engineering division in Physical Design domain

ASIC SynthesisLECPhysical DesignSTAPVIR drop

Vlsi system design centre, msrsas - coventry university

Project Engineer, Researcher, Corporate Trainer, and Mentor

May 2008 – Mar 2017 · 8 yrs 10 mos · Bengaluru, Karnataka, India

ASIC Physical Design
Analog, digital and mixed signal circuit design and layout Implementation
Standards cell library development
Memory design & Implementation
50+ Post graduate level projects in STD cells, Memory, analog, mixed signal and digital processor design for working engineers in leading semiconductor industries like Intel, AMD, ARM, IBM, Samsung, Microchip, TI, etc.,
Master Engineering curriculum as a board of subject
Corporate training for ASIC physical design and custom layout design domain
Research projects in Analog, digital and mixed signal domain