Kunal Gupta

Software Engineer

Delhi, India8 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in SystemVerilog and UVM for verification IP development.
  • Proven track record in designing complex verification architectures.
  • Hands-on experience with multiple communication protocols.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in IP development and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)Verilog

Other Skills

Verification IP DevelopmentAPBAXIUARTUSB4DisplayPortC (Programming Language)C++VHDLMatlabOrCAD Capture CISProteus

Experience

8 yrs 6 mos
Total Experience
4 yrs 3 mos
Average Tenure
5 yrs 4 mos
Current Experience

Qualcomm

3 roles

Senior Lead Engineer

Dec 2024 – Present · 1 yr 4 mos

Senior Engineer

May 2023 – Nov 2024 · 1 yr 6 mos

Senior Engineer

Oct 2020 – Apr 2023 · 2 yrs 6 mos

Mentor graphics

2 roles

Senior Member Of Technical Staff

Jan 2019 – Sep 2020 · 1 yr 8 mos · Noida, Uttar Pradesh, India

  • Verification IP Development using System Verilog and UVM Testbench Architecture
  • Protocols - APB, AXI, UART, USB4 Logical Layer, DisplayPort
SystemVerilogUniversal Verification Methodology (UVM)Verification IP Development

Member Of Technical Staff

Jun 2017 – Dec 2018 · 1 yr 6 mos · Noida, Uttar Pradesh, India

  • Verification IP Development using System Verilog and UVM Testbench Architecture
  • Protocols - DisplayPort v1.4
SystemVerilogUniversal Verification Methodology (UVM)Verification IP Development

Centre for fire, exlosive and environment safety, drdo

Summer Intern

Jun 2016 – Jul 2016 · 1 mo · Greater Delhi Area

  • Summer Internship at Center for Fire, Explosive and Environment Safety, (CFEES) DRDO
  • Project 1: Implemented 8-bit UART using Verilog.
  • Project 2: Designed and implemented GSM signal jammer which blocks the mobile signals in 900MHz
  • frequency band. It can be used at libraries, conference rooms etc..

Solid state physics laboratory, drdo

Winter Intern

Dec 2015 – Dec 2015 · 0 mo · Greater Delhi Area

  • Winter Internship at Solid State Physics Laboratory (SSPL), DRDO
  • Project: Read and wrote data to/from SD Card.

Education

Delhi Technological University

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2013 – Jan 2017

Kulachi Hansraj Model School

Non Medical (CBSE)

Jan 1999 – Jan 2013

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