Ritika ..

Software Engineer

Delhi, India15 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in advanced SoC implementation across multiple nodes.
Proven track record in driving multi-million-gate designs to tape-out.
Skilled in mentoring junior engineers and leading complex projects.

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in advanced SoC implementation.

Contact

ritika29verma@gmail.com LinkedIn

Skills

Core Skills

Physical DesignTiming Closure

Other Skills

Synopsys PrimetimePlace & RouteStatic Timing AnalysisTCLPerlClock Distribution

About

Professional Summary Senior Physical Design Engineer with 9+ years of hands-on experience in advanced SoC implementation across 10nm, 7nm, 5nm, and 4nm nodes. Proven track record in netlist-to-GDSII flows, static timing analysis (STA), clock tree synthesis (CTS), place & route (P&R), and timing closure. Adept at navigating PPA trade-offs, driving multi-million-gate designs to tape-out, and mentoring junior engineers. Demonstrated success in leading complex projects through collaboration across cross-functional teams. Core Competencies • Netlist-to-GDSII Flow Development • Physical Design: Floorplanning, Placement, CTS, Routing • Timing Signoff & STA • Clock Tree Design: Multi-Voltage, Multi-Domain • Power/Performance/Area Optimization (PPA) • Physical Verification (DRC/LVS) • Scripting (TCL, Perl) • EDA Tools: PrimeTime, Innovus, ICC2 • PD Methodologies (PD-TFM, Flow Bring-Up)

Experience

15 yrs 5 mos

Total Experience

5 yrs 1 mo

Average Tenure

9 yrs 8 mos

Current Experience

Qualcomm

4 roles

Staff Engineer

Promoted

Dec 2023 – Present · 2 yrs 4 mos

Delivered multiple successful tape-outs across advanced nodes by implementing robust CTS solutions, using custom H-tree architectures.
Optimized power/performance trade-offs on multi-clock, low-power designs. Enhanced Quality of Results (QoR) by evaluating multiple floorplan strategies and fine-tuning PPA switch settings in PNR tools, leading to significant improvements in congestion, timing, and utilization metrics.
Applied congestion analysis techniques including max density control and blockage insertion to identify and alleviate high-density regions, reducing congestion issues and optimizing area usage (area saving).
Performed timing closure and STA efforts on high-performance SoC designs at lower tech nodes, achieving timing closure ahead of schedule.
Spearheaded netlist-to-GDS flow optimizations, reducing design cycle time via improved automation. Automated ECO flow using TCL/Perl scripts, accelerating tapeout cycles and reducing manual error.

Synopsys PrimetimePlace & RouteStatic Timing AnalysisPhysical DesignTiming Closure