Sanjay Singh Yadav

Software Engineer

Hyderabad, Telangana, India11 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in VLSI CAD and Python for semiconductor design.
  • Proven track record in FPGA design analysis and timing closure.
  • Hands-on experience with various memory interfaces and automation.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and FPGA technologies.

Contact

Skills

Core Skills

Vlsi CadPython

Other Skills

Customer EngagementProduct DevelopmentVerilogCC++VHDLMatlabMathematicaLabVIEWCadenceOPNETGNU RadioXilinx ISEHTMLWARP

About

Experiences in semiconductor EDA field, presently working for Xilinx India • Responsible for Developing, Maintaining and adding new features in the Automation Infrastructure using PYTHON,PERL,CSH and TCL • Expertise in creating,randomizing test cases and testplans based on frequency ,Data width etc for various memory Interfaces like DDR3,DDR4,RLDRAM3,QDRII and QDRIV using PERL scripting Language • Responsible for writing RTL (Verilog Codes) used for automation,Testing features of the memory interfaces and debug of Hardware flow of various memory interfaces using XILINX IPs like VIO(Virtual Input/Output) and ILA (Internal Logic Analyser) • Expertise in automation of Hardware flow to validate memory interfaces like DDR3,DDR4,RLDRAM3,QDRII and QDRIV with XILINX Ips like VIO ( Virtual Input/Output Interface) and ILA (Internal Logic Analyser) using TCL scripting Language. • Good Knowledge in Verilog, System Verilog, Perl, TCL and Shell scripting. • Hands on experience on Perforce, JIRA • Hands on experience on Linux Operating System. • Result oriented, self-driven, highly motivated and hungry to learn new technologies, methodologies, strategies and processes

Experience

11 yrs 6 mos
Total Experience
3 yrs 10 mos
Average Tenure
4 yrs 2 mos
Current Experience

Amd

2 roles

Senior Silicon Design Engineer

Promoted

Nov 2023Present · 2 yrs 6 mos · Hyderabad, Telangana, India

  • Developing customer focussed tools/commands to optimize implementation solutions using Tcl/Python/Perl/Shell-scripting
  • Analyzing performance and make implementation choices to optimize timing
  • Analyze and optimize design for power efficiency and power integrity
  • Work with verification and physical design teams to achieve high quality design and successful tape out
  • Skills: VLSI CAD · Python (Programming Language) · Customer Engagement · Product Development · Verilog
VLSI CADPythonCustomer EngagementProduct DevelopmentVerilog

Silicon Design Engineer-2

Mar 2022Nov 2023 · 1 yr 8 mos · Hyderabad, Telangana, India

Xilinx

3 roles

Design Engineer-2

Nov 2021Feb 2022 · 3 mos

  • FPGA Design Analysis and Timing Closure of Customer Designs. Benchmarking Software tool for QoR Performance.

Design Engineer-1

Dec 2017Oct 2021 · 3 yrs 10 mos

Intern

Jan 2017Nov 2017 · 10 mos

National institute of technology, tiruchirappalli

Research Student

Jul 2014Dec 2016 · 2 yrs 5 mos · Tiruchchirāppalli Area, India

  • Objective: Performance Evaluation of Cognitive Radio System
  • Progress: Implemented the cognitive radio system using various hardware kits USRP (Universal
  • Software Radio Peripheral)/ WARP (Wireless Open-Access Research Platform)/ RTL-SDR
  • (RTL2832U) which solves the problem of spectrum congestion. Still experimenting for energy
  • efficient VLSI architecture for cognitive radio.

Education

National Institute of Technology, Tiruchirappalli

Master's degree — Electronics and Communications Engineering

Jan 2014Jan 2016

Rajiv Gandhi Prodyogiki Vishwavidyalaya

Bachelor of Engineering (BE) — Electronics and Communications Engineering

Jan 2009Jan 2013

ST. FRANCIS HER. SEC. SCHOOL

XII

Jan 1997Jan 2009

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