Kaluri Praveen Raja

Software Engineer

Hyderabad, Telangana, India4 yrs 5 mos experience
Highly Stable

Key Highlights

  • Expert in Universal Verification Methodology and SystemVerilog.
  • Strong background in VLSI design and embedded systems.
  • Proven leadership and public speaking skills.
Stackforce AI infers this person is a VLSI and ASIC design expert with strong verification skills.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

Microsoft PowerPointVerilogC (Programming Language)LeadershipPublic SpeakingCadence VirtuosoH-SpiceXilinx ISENI MultisimPython (Programming Language)Very-Large-Scale Integration (VLSI)VLSI CAD

Experience

4 yrs 5 mos
Total Experience
1 yr 9 mos
Average Tenure
10 mos
Current Experience

Amd

Senior silicon design engineer

Jul 2025 – Present · 10 mos · Hyderabad · Hybrid

Synopsys inc

3 roles

Senior Engineer ASIC Digital Design

Jan 2024 – Jul 2025 · 1 yr 6 mos

ASIC Digital Design Engineer II

Apr 2022 – Jan 2024 · 1 yr 9 mos

Universal Verification Methodology (UVM)SystemVerilog

RTL Design and Verification Engineer Intern

Jul 2021 – Mar 2022 · 8 mos

Universal Verification Methodology (UVM)SystemVerilog

Nit raipur

Teaching Assistant

Jul 2019 – Jul 2021 · 2 yrs · Raipur, Chhattisgarh, India

Tata consultancy services

Intern

Dec 2017 – Apr 2018 · 4 mos · Visakhapatnam, Andhra Pradesh, India

Bharat sanchar nigam limited

Summer Intern

May 2016 – May 2016 · 0 mo

Education

NIT Raipur

M.TECH — VLSI DESIGN AND EMBEDDED SYSTEMS

Jan 2019 – Jan 2021

Gayatri Vidya Parishad College of Engineering (Autonomous), 530048(CC-13)

Bachelor of Technology — Electronics and Communications Engineering

Jan 2014 – Jan 2018

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