Ayush Dixit — Software Engineer

I’m Ayush Dixit, a semiconductor professional specializing in post-silicon validation, embedded systems engineering and firmware development. My expertise spans functional and performance validation across SOC IP's , memories (LPDDR3/4/5) and Gen4/5 SoCs (down to 3nm nodes), with hands-on experience in Silicon Bring-Up, embedded C driver development, and system validation flows. Beyond hardware, I bridge the gap with software by applying Python automation and AI/ML techniques to accelerate debug, streamline workflows, and enable smarter validation strategies. My masters research also focused on applying machine learning to optimize random verification, an area I continue to explore and apply in my workflows. 🔧 𝐂𝐨𝐫𝐞 𝐄𝐱𝐩𝐞𝐫𝐭𝐢𝐬𝐞 👉Post-Silicon Validation (Core SOC IPs, CRS. FSS, DDR PHY, bring-up planning, test planning) 👉Embedded C / Firmware Development 👉SystemVerilog/UVM (pre-silicon verification) 👉Python Automation & Tooling 👉AI/ML for Semiconductor Validation 📌 𝐀𝐜𝐡𝐢𝐞𝐯𝐞𝐦𝐞𝐧𝐭𝐬 🏆 Best Paper Award – NXP Global Validation Summit 🎓 10+ Certifications (Embedded Systems, AI/ML, Product Mgmt) 🥇 HackerRank Python Gold Badge 🎯 GATE AIR 532 (ECE) 📖 Technical blogs featured on Medium & leading publications 🌱 𝐁𝐞𝐲𝐨𝐧𝐝 𝐖𝐨𝐫𝐤 🔹 Writing & Blogging | 🔹 Teaching | 🔹 Fitness | 🔹 Travel 1:1 Consultations (Topmate): https://topmate.io/ayushdixitpage/ 𝐄𝐦𝐚𝐢𝐥: ayushdixit777@gmail.com 𝐁𝐥𝐨𝐠: medium.com/@ayush_dixit

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in post-silicon processes and AI-driven automation.

Location: Noida, Uttar Pradesh, India

Experience: 11 yrs 5 mos

Skills

Silicon Validation
Post-silicon Validation

Career Highlights

Expert in post-silicon validation and embedded systems.
Award-winning researcher with a focus on AI/ML in validation.
Proficient in Python automation for streamlined workflows.

Work Experience

AMD

Member of Technical Staff (1 mo)

NXP Semiconductors

Lead Design Validation Engineer (1 yr 3 mos)

Qualcomm

Post Silicon Validation Engineer (3 yrs 5 mos)

Interim Engineering Intern : Pre-Silicon Verification (10 mos)

IIT Indore Training and Placement Cell

Placement Coordinator (1 yr 7 mos)

Indian Institute of Technology, Indore

Teaching Assistant (1 yr 2 mos)

Skill Planet

Subject Matter Expert (1 yr 10 mos)

Thankship

Content creator (5 mos)

Ericsson

Assistant Engineer (1 yr 7 mos)

Texas Instruments

Project Intern(Embedded Electronics) (2 mos)

Thinnkware

Campus recruitment Ambassador (6 mos)

GNIX(Electronics Society of GCET)

General Secretary (1 yr)

Pristine Info Solutions

Campus Ambassador (1 yr 1 mo)

Education

Master of Technology - MTech at Indian Institute of Technology, Indore

Product Management at Indian School of Business

Bachelor of Technology (B.Tech.) at Galgotia College of Engineering and technology

at CMS Gomtinagar

Ayush Dixit

Software Engineer

Noida, Uttar Pradesh, India11 yrs 5 mos experience

Highly Stable

Key Highlights

Expert in post-silicon validation and embedded systems.
Award-winning researcher with a focus on AI/ML in validation.
Proficient in Python automation for streamlined workflows.

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in post-silicon processes and AI-driven automation.

Contact

Skills

Core Skills

Silicon ValidationPost-silicon Validation

Other Skills

Joint Test Action Group (JTAG)SystemVerilogAnalog CircuitsLogic AnalyzerDDR4DDR3 SDRAMDebuggersUVMMeasurement ToolsASIC DesignSilicon Bring-UpDDR FirmwareJTAGPython scriptingOscilloscopes

About

Experience

11 yrs 5 mos

Total Experience

1 yr 4 mos

Average Tenure

1 mo

Current Experience

Amd

Member of Technical Staff

Mar 2026 – Present · 1 mo

Firmware Development Engineer - Platform Architecture Team

Nxp semiconductors

Lead Design Validation Engineer

Nov 2024 – Feb 2026 · 1 yr 3 mos · Noida · On-site

Research & Development - Performance & Functional Design Validation (Post-Silicon)

Qualcomm

2 roles

Post Silicon Validation Engineer

Jun 2021 – Nov 2024 · 3 yrs 5 mos

Silicon Validation Engineer - DDR Subsystem and Mixed Signal Systems (MS-SVE)
Part of the Post Silicon DDR-PHY Bring-up Team (Design and Validation)
Required to create, define and develop system validation environment & test suites optimized for a CPU, DDR or its subsystems like memory controller, PHY(Physical Layer) and other modules of given complexity.
I am responsible for the development of test plans, execution of validation plans/ coverage, and debug of failures.
My work requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features.
Understanding and debugging legacy codes in C and C++ for different MSM's/projects concerning DDR-PHY Bring-up.
☛ Silicon Validation
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
● Work on the latest LPDDR technologies (LPDDR4, 4x, 5, 5x) across varied platforms of Mobile, Auto, Compute and IoT chipsets.
● Work on Oscilloscopes and Data eyes for electrical and functional validation of DDR-PHY
● Own and maintain DDR Firmware (C language) to tune key parameters for high-speed communication on LPDDR protocol. Validate DDRPHY block with the help of DDR Firmware over JTAG interface using Lauterbach Trace32.
● In Post-Silicon, work with key stakeholders in VI, ATE, Bench and Software teams for successful Bring-Up of DDRPHY block, from SoD to CS.
● Make sure timing, voltage and other parameters match with the official JEDEC specs.
● Work with Design and DV during Pre-Silicon timeline to understand design changes / features to validate on Silicon.
☛ Programming / Tool Development
‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾
● Bring-Up new APIs for DDR Training in C language.
● Linux Shell scripting for automation and makefile customizations.
● Python scripting for Volume Data analysis, CSV file optimizations and automating Post-Si experiments for triage.

Joint Test Action Group (JTAG)SystemVerilogAnalog CircuitsLogic AnalyzerDDR4DDR3 SDRAM+7

Interim Engineering Intern : Pre-Silicon Verification

Jul 2020 – May 2021 · 10 mos

Pre-Silicon Verification
Designing an Artificial Neural Network to optimise Random Verification.
Implementation of Machine Learning in the Design/Verification environmement.
Working on Verification methodologies, architecture, and UVM constructs to build scalable and reusable verification collaterals.
Collaborate with the design teams to develop robust verification strategy, defining test plans, test writing, and debug in accordance with IP spec.
Pre-Silicon Verification

Iit indore training and placement cell

Placement Coordinator

Sep 2019 – Apr 2021 · 1 yr 7 mos

Indian institute of technology, indore

Teaching Assistant

May 2019 – Jul 2020 · 1 yr 2 mos · Indore, Madhya Pradesh, India

M.Tech - Communication, signal processing and AI

Skill planet

Subject Matter Expert

Jun 2017 – Apr 2019 · 1 yr 10 mos

Handling projects involving UI/UX, Verilog, Software development cycle, protocol stacks, Embedded C and Telecom BSS.

Thankship

Content creator

Jan 2016 – Jun 2016 · 5 mos · London, United Kingdom

Content Writing for featured articles on Thankship.com. Great intiative which fosters gratitude in the corporate and social sector.

Ericsson

Assistant Engineer

Oct 2015 – May 2017 · 1 yr 7 mos · Gurgaon, Haryana, India

MPBN/RAN Engineer -: 2nd LA Back Office
Dealt with monitoring tools like network packet capture tools like Wire-shark, cisco packet tracer etc.
Troubleshooting both the voice and data over ip technologies environment.
Replacing branch hardware with new 2851 routers and 2960 switches.
Performing security audits of perimeter routers, identifying missing ACL’s
Troubleshooting of complex LAN/WAN infrastructure, including routing protocols EIGRP, OSPF & BGP.

Texas instruments

Project Intern(Embedded Electronics)

Jan 2015 – Mar 2015 · 2 mos · New Delhi Area, India

Thinnkware

Campus recruitment Ambassador

Jul 2014 – Jan 2015 · 6 mos · Greater noida

Gnix(electronics society of gcet)

General Secretary

Aug 2013 – Aug 2014 · 1 yr · Galgotia college of Engineering and Technology

Headed the technical society of Galgotias Educational Institutions. To know more about Gnix check out the fb page-:
http://goo.gl/Hs9Pt7
And the slideshow-:
http://goo.gl/CUwvgk