Vidhun U K

Software Engineer

Bengaluru, Karnataka, India12 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in IP verification and digital design.
  • Strong background in SOC and block level verification.
  • Proficient in UVM methodologies and AXI protocols.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in digital design and validation methodologies.

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Skills

Core Skills

VerificationDigital DesignValidationTesting

Other Skills

ASICAXI protocolsAnalog test coverageCDigital ElectronicsFPGAIEEE 802.3 specificationIntegrated Circuit DesignLinuxLogic SynthesisPost Silicon ValidationProgrammingSOC VerificationSQLSoC

About

• Currently working in IP Verification for Memory team. • Have experience in Verilog, SystemVerilog, UVM methodologies and AXI protocols. • Completed M.Tech in Microelectronics and VLSI Design,National Institute of Technology, Calicut with 8.54 cgpa • Completed 10 month Internship in STMicroelectronics, Greater Noida. .

Experience

Samsung semiconductor india

Senior Staff Engineer

Dec 2015Present · 10 yrs 3 mos · Bengaluru, Karnataka, India

VerilogSystemVerilogUVMAXI protocolsVerificationDigital Design

Amd

Design Engineer 1

Jul 2013Oct 2015 · 2 yrs 3 mos · Hyderabad, Telangana, India

  • Worked in both SOC and Block level Verification for Video codec team.
  • Works involve integration of IP at Soc Level,Test case writing and test bench development which include development of uvm components, scoreboard, reference model cover points etc.
SOC VerificationTest case writingTest bench developmentUVM componentsVerificationDigital Design

Stmicroelectronics

Intern

Jul 2012May 2013 · 10 mos · Noida, Uttar Pradesh, India

  • Worked as Trainee in High speed serial link validation team at Technology Research & Development Department. The work involved Post Silicon Validation of Gigabit Ethernet PHY, exhaustive analog test coverage of IEEE 802.3 specification with high end equipments like Oscilloscope, Network Analyzer etc & support to UNH certification of STMicroelectronics developed IP.
Post Silicon ValidationAnalog test coverageIEEE 802.3 specificationValidationTesting

Education

National Institute of Technology Calicut

m.tech — Microelectronics and VLSI

Jan 2011Jan 2013

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