Jul 2015 – Oct 2023 · 8 yrs 3 mos · Bangalore · On-site

• + Micro architecture, RTL coding, Low power design, UPF, Lint, CDC, Synthesis
• + ARM NIC, Sonics NOC generation for main interconnect in multiple projects with varying requirements, performance and complexity
• + ARM based CPU integration, address map definition, TrustZone, debug architecture along with integration of technology components needed for SoC like IOPAD, memories, LDO, SWREG, PLL, PVTMON, OTP and AVS
• + Experience with EDA tools like VCS, Spyglass, Design compiler, Prime time, VC-static, Conformal Low power
• + Good knowledge on AMBA AXI/AHB/APB bus protocols and low speed interfaces like I2C, (Q)SPI, UART
• Projects:
• + CXL based memory expander SoC
• + Hardware Video Accelerator, Gen2
• + Hardware Video Accelerator, Gen1
• + VOIP/Wireless audio SoC
• + Embedded SoC for LED lighting and Industrial applications

Jan 2012 – Jul 2015 · 3 yrs 6 mos · Bangalore · On-site

• Roles and Responsibilities:
• + Writing functional specification, micro-architecture design of various sub blocks, feature enhancements, optimization, performance improvement for 1G and 10G Ethernet controller IP having multi channel DMA controller and AMBA interface
• + Design and code reviews
• + RTL coding of various sub blocks/features using verilog HDL, design constraints using SDC
• + Involved in other design related activities that includes LINT, CDC checking, functional simulation, synthesis, LEC etc.
• + Test plan and directed testcase development
• + Optimizing the IP for timing improvement in order to fit into FPGA for hardware prototyping
• + Knowledge of PCS for 10G/40G ethernet
• + Familiar with various protocols that includes TCP, UDP, IPv4, IPv6, IEEE 1588 Precision Time Protocol (PTP)
• + Familiar with Data Center Bridging (DCB) and Audio Video Bridging (AVB) concepts, Receive Side Scaling (RSS)
• + AMBA - AXI, AHB, APB
• + Basic TCL scripting
• Technology/Protocols:
• + Ethernet 10/100/1000, 10G, 40G MAC with QoS support and multi channel DMA controller and PCS
• + IEEE 1588 (PTP)
• + TCP/IP
• + AMB AHB/AXI/APB
• + DCB
• + AVB

Nov 2008 – Jan 2012 · 3 yrs 2 mos · Bangalore

• Roles and Responsibilities:-
• + Successfully completed multiple FPGA design projects most of which are started from the scratch
• + Performed as individual and team contributor
• + Responsible for requirement gathering and requirement capture
• + Supporting hardware design team during FPGA selection and pin planning and clocking
• + Responsible for preparing PLD design document that includes the architecture and micro architecture definition
• + Responsible for design and code reviews
• + Mentoring and assigning sub-blocks development to team members and review
• + RTL coding of critical sub blocks using VHDL/verilog and integration of all the sub blocks and IP's (DDR, Ethernet, etc)
• + Setting up basic functional verification environment and performing functional verification
• + Setting up the constraints and implementation on the target FPGA
• + Board bring up and interface validation
• + On board testing and debugging using Integrated Logic analyzers (chipscope)
• + Integration testing and acceptance testing at customer sites
• Technology:-
• + Xilinx Virtex 5, Spartan 6 FPGA architectures
• + Altera Stratix III and Arria V GX architectures
• + Telemetry, Radar signal processing, SS7
• + DDR, Ethernet, UDP/IP
• + Hardware in Loop (HIL)
• + VHDL, Verilog
• + Knowledge of high speed board design and signal integrity
• Tools/Environment:-
• + Xilinx ISE, EDK and SDK
• + Altera Quartus
• + Modelsim ISE
• + Chipscope
• + Digital Storage Oscilloscope
• + Spectrum Analyzer
• + Logic Analyzer

Sep 2005 – Nov 2008 · 3 yrs 2 mos · Bangalore

• Worked as a DVT and HQA engineer in various telecom wireline access products such as DLC/DSLAM, IP DSLAM, FTTN, FTTP
• Roles and Responsibilities:-
• + Responsible for failure analysis of multiple telecom wireline access systems built on custom ASIC’s and have good knowledge at system level
• + Responsible for preparation of DVT test plan, test execution and preparation of DVT test report.
• Involved in test plan reviews and weekly status meeting conducted by customer.
• + Developed Labview application for automating vdsl2 performance tests.
• + Involved in DVT and HQA test execution at customer’s lab in Lowell, USA for six months and guided off shore team for DVT and HQA.
• + Prepared HQA test plan for GR909 POTS testing and established a test setup in offshore lab and involved in test execution.
• + Hands on experience using test equipments such as smartbits, adtech, abacus, PCM4, SAGE, Spirent DLS 8100 vdsl2 loop simulator, etc.
• + Hands on experience using spectrum analyzer and DSO
• + Hands on experience using IXP23xx Roadrunner reference board containing IXP2350 network processor and Infineon Easy 4270 reference board containing Convergate-C network processor, Geminax-D ADSL2+ chipset, Vinetic voice chipset
• + Gained knowledge of micro engine architecture and programming the microengine using microcode
• + Gained knowledge of INTEL IXP2350 network processor architecture and Intel IXA framework
• Technology/Protocols:-
• + BPON/GPON
• + ADSL2+, VDSL, VDSL2
• + SONET
• + POTS
• + T1
• + ATM
• + INTEL IXP 23XX network processor
• + Infineon Easy 4270 reference kit
• Tools/Environment:-
• + Smartbits Ethernet traffic generator/analyzer
• + Adtech ATM traffic generator/analyzer
• + Abacus bulk call generator,
• + PCM4, SAGE POTS/T1 analyzer
• + Spirent DLS 8100 VDSL2 loop simulator and noise injector
• + Infineon Easy 4270 with Convergate-C network processor and Geminax-D ADSL2+ chipset
• + Labview