R

Raghav Yerramreddikalva

Engineering Manager

Bengaluru, Karnataka, India27 yrs 2 mos experience
Highly Stable

Key Highlights

  • Proven leadership in engineering management at Intel.
  • Expertise in VLSI and ASIC design methodologies.
  • Strong background in timing analysis and physical design.
Stackforce AI infers this person is a semiconductor engineering expert with a focus on VLSI and ASIC design.

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Skills

Core Skills

SocAsic

Other Skills

Static Timing AnalysisLogic SynthesisVLSIRTL designTimingEDAPhysical DesignTiming ClosureICTCLSemiconductorsLow-power DesignIntegrated Circuit DesignCMOSProcessors

Experience

27 yrs 2 mos
Total Experience
27 yrs 2 mos
Average Tenure
27 yrs 2 mos
Current Experience

Intel corporation

2 roles

Engineering Manager

Promoted

Apr 2014Present · 12 yrs · Greater Bengaluru Area

SoCASICStatic Timing AnalysisLogic SynthesisVLSIRTL design+13

Senior Design Engineer

Jan 1998Mar 2013 · 15 yrs 2 mos

Education

The University of Toledo

M.S. — VLSI Design

Jan 1997Jan 1998

Andhra University

B.E. — Electronics and Communication Engineering

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