Harini SR — Software Engineer
Worked on 5nm and 4nm successful tape out. DRC cleanup and pattern generation for SAF, TDF, SDD and Bridging at block level and chip-top level. Generated Stuck-at and Transition patterns from block level and Pattern retargeted at SoC level. Pattern simulations in both timing and no timing environment at block level and SoC level. STIL to TST conversion for Tester. Supported for post silicon bring up and debugging.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on DFT and ASIC development.
Location: Bengaluru, Karnataka, India
Experience: 7 yrs 4 mos
Skills
- Design For Test
- Vlsi
Career Highlights
- Expert in DFT with extensive experience in VLSI.
- Successful tape-out experience at 5nm and 4nm technology nodes.
- Proficient in pattern generation and simulation for SoC.
Work Experience
MediaTek
Staff DFT Engineer (2 yrs 9 mos)
Senior DFT Engineer (1 yr 7 mos)
DFT Engineer (1 yr 5 mos)
Dhole Patil Education Societys Dhole Patil College of Engineering,Pune
Assistant Professor (8 mos)
IISc, bangalore
Intern (11 mos)
Education
MTech - Master of Technology at Visvesvaraya Technological University
