Vinav Patel — Software Engineer

- Hands-on ASIC Physical Design Implementation experience on Fusion Compiler,ICC2 and Innovus. - Involved in 10+ successful physical design tape outs of multi-million gates complex chips of Networking, Graphics and Mobile Processor Chips in 3nm, 5nm, 7nm,16nm and 28nm technologies. - Expertise in ASIC Physical design from RTL to GDSII which includes Floorplan, PnR, Timing Closure, - ECO Implementation , VCLP, Formality, PV and all Sign Off Checks. - Exposure of Full Chip Work, SubSystem or IP Execution, Block Level Execution - Recognized with Pat on Back & Core Value Award for handling the critical blocks and best support in the project execution multiple times within Organization :: PROFESSIONAL SKILLS: - PnR : Innovus, ICC2, Fusion Compiler - STA : Primetime (PT) - Extraction: StarRC - FEV: Conformal - Power Analysis: RedHawk - Physical Verification : IC Validator, Caliber - Scripting Languages: Tcl

Stackforce AI infers this person is a Semiconductor Physical Design Engineer with extensive ASIC expertise.

Location: Bengaluru, Karnataka, India

Experience: 12 yrs 1 mo