Akshay Garje

Software Engineer

Bengaluru, Karnataka, India2 yrs 9 mos experience
Highly Stable

Key Highlights

  • Senior Engineer with expertise in Verilog and SystemVerilog.
  • Strong foundation in VLSI design from a reputed institution.
  • Passionate about technology and continuous improvement.
Stackforce AI infers this person is a VLSI Design Engineer with a focus on hardware description languages.

Contact

LinkedIn

Skills

Core Skills

VerilogSystemverilogPython

Other Skills

TeamworkPython (Programming Language)CInternet of Things (IoT)Data StructuresPerlTCL

About

"I am a design Senior Engineer with MediaTek, working in the STA team. I bring with me knowledge of Verilog hardware language and a strong passion for technology. When I'm not at work, you'll find me playing sports and maintaining a healthy work-life balance. I believe in putting in the extra effort to achieve my goals and constantly striving for excellence."

Experience

2 yrs 9 mos
Total Experience
2 yrs 9 mos
Average Tenure
2 yrs 9 mos
Current Experience

Mediatek

2 roles

Senior Synthesis Engineer

Jul 2023 – Present · 2 yrs 9 mos · Banglore

VerilogSystemVerilogTeamwork

Intern

Sep 2022 – Jul 2023 · 10 mos · Banglore

Python (Programming Language)Python

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI DESIGN

Aug 2021 – Aug 2023

Pune Institute of Computer Technology

Bachelor of Engineering — Electronics and Communications Engineering

Jan 2015 – Jan 2019

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