Balakrishna Chaitanya

Software Engineer

Bengaluru, Karnataka, India6 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in RTL Design and Digital Design.
Proficient in Verilog and SystemVerilog.
Strong background in Python and Perl automation.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and digital design.

Contact

Skills

Core Skills

Rtl DesignDigital Design

Other Skills

VerilogPythonPerlSystemVerilogCCadence VirtuosoTCLRTL CodingPerl Automation

Experience

6 yrs 10 mos

Total Experience

3 yrs 5 mos

Average Tenure

3 yrs 8 mos

Current Experience

Amd

Sr Silicon Design Engineer

Sep 2022 – Present · 3 yrs 8 mos · Bengaluru, Karnataka, India

VerilogDigital designPythonPerlRTL DesignSystemVerilog+5

Cadence design systems

2 roles

Design Engineer II

Jun 2021 – Aug 2022 · 1 yr 2 mos

DDR Memory Controller

Design Engineer I

Jun 2019 – Jun 2021 · 2 yrs

Electronics corporation of india limited (ecil), department of atomic energy, government of india.

Intern

May 2017 – Jun 2017 · 1 mo · Hyderabad, Telangana, India

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — Microelectronics

Vellore Institute of Technology

Bachelor of Technology - BTech — Electronics and Communications Engineering

Jan 2015 – Jan 2022

Narayana Junior College

MPC

Jan 2013 – Jan 2015

Vignan Global Gen School

Jan 2009 – Jan 2013

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