Vinay Kumar Prajapati

Software Engineer

Bengaluru, Karnataka, India11 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI characterization and digital design.
Proficient in Perl and Tcl-Tk scripting for automation.
Strong educational background in Embedded Systems.

Stackforce AI infers this person is a VLSI Engineer with expertise in digital design and characterization.

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Skills

Core Skills

CharacterizationDigital Design

Other Skills

Timing characterizationLeakage Power characterizationDynamic Power simulationDigital characterizationModeling Low Power AttributesPrimetimeMAT10 Views GenerationValidationPhysical views implementationValidation of functional viewsTiming analysisLeakage analysisPerlTcl-TkShell Scripting

About

Experienced Senior Engineer with a demonstrated history of working in the VLSI industry. Skilled in Characterization (Serdes blocks, IOs, ADC, DAC, PLL), Layout Versus Schematic (LVS), Tcl-Tk, PERL etc.. Strong engineering professional with a Master’s Degree focused in Embedded System from School Of Electronics, DAVV Indore.

Experience

11 yrs 6 mos

Total Experience

5 yrs 9 mos

Average Tenure

7 yrs 3 mos

Current Experience

Qualcomm

3 roles

Staff Engineer

Promoted

Dec 2024 – Present · 1 yr 4 mos

Senior Lead Engineer

Dec 2021 – Dec 2024 · 3 yrs

Senior Engineer

Jan 2019 – Dec 2021 · 2 yrs 11 mos

Stmicroelectronics

3 roles

Sr. Design En

Promoted

Jan 2018 – Jan 2019 · 1 yr

1. Responsible for the Timing, Leakage Power, Dynamic Power, Switch DC Current, RON characterization for EPOD (Embedded POwe Distribution) libraries used in low power flow.
2. Digital characterization using primetime for different IP's: ADC/DAC/PLL/OSC/Sensors.
3. Timing, Leakage Power and Dynamic power simulation for IO's and AMS IP's using ELDO simulator.
4. Responsible for the correct modelling of Low Power Attributes in STF.

Timing characterizationLeakage Power characterizationDynamic Power simulationDigital characterizationModeling Low Power AttributesCharacterization+1

Design Engineer

Sep 2015 – Jan 2018 · 2 yrs 4 mos

MAT10 Views Generation And Validation.

MAT10 Views GenerationValidation

Intern

Jul 2014 – Jun 2015 · 11 mos · Greater Noida

Title: Physical views implementation in 14FDSOI
Description:
Working in IO group for various MAT10 views generation and validation of functional,
timing, power and physical implementation views for various I.Ps and hard macros
designed in Design platform group.
Generation as: physical (cdl, gds), LEF (SOC, SIP and signoff), Libs, SYNOPSYS (layout and
FRAM), ICPACK etc.
Validations as: LVS, DRC etc.
Also to analyze the changes in 14FDSOI with respect to 28FDSOI from manufacturing
aspects and also from physical views aspects (especially LEF and FRAM), and according
with these changes, design a tool using scripting language as PERL or TCL.
Title: Timing, leakage and Noise characterization of Different IOs.
Description:
Performed timing, leakage and noise analysis of different IOs (General Purpose Analog
IOs, I2C, DDR3 /4) to meet the pre-defined specification on different voltage, process
conditions and leakage.