Skills

• Static Timing Analysis
• Logic Synthesis

Career Highlights

• Experienced in Static Timing Analysis and Logic Synthesis.
• Proficient in multiple EDA tools including Synopsys and Cadence.
• Strong background in ASIC design and semiconductor technologies.

Work Experience

Education

Bachelor’s Degree at Institution of Engineers (India)

Diploma at Pusa Polytechnics

High school at Army Public School, New Delhi