Raffiq S.

Software Engineer

Bengaluru, Karnataka, India6 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in ASIC verification with UVM and SystemVerilog.
  • Proficient in assertion-based verification methodologies.
  • Strong background in digital design and verification.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification methodologies.

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Skills

Core Skills

Universal Verification Methodology (uvm)Systemverilog

Other Skills

Assertion Based VerificationDigital DesignsDesign Verification TestingRTL DesignMicrosoft ExcelC (Programming Language)MatlabVerilog

About

Experienced ASIC Verification with a history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Design(rtl), perl, assertion based verification. knowledge in questa, cadence xcelium tool nd verdi.

Experience

6 yrs 9 mos
Total Experience
4 yrs 1 mo
Average Tenure
6 yrs 9 mos
Current Experience

Samsung semiconductor

Staff Engineer

Dec 2024Present · 1 yr 4 mos · Bengaluru, Karnataka, India

Mediatek

2 roles

Senior Engineer

Jul 2022Dec 2024 · 2 yrs 5 mos

asic verification

Jul 2019Present · 6 yrs 9 mos

Universal Verification Methodology (UVM)SystemVerilogAssertion Based Verification

Education

GMR Institute of Technology (GMRIT), GMR Nagar, Rajam, Srikakulam Dt.,-532127 (CC-34))

Bachelor of Technology - BTech

Jan 2014Jan 2018

BITS Pilani Work Integrated Learning Programmes

Master of Science - MS — Microelectronics

Jan 2021Nov 2022

Maven silicon

Vlsi-front end design and verification

Jul 2018Jun 2019

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