Raffiq S. — Software Engineer
Experienced ASIC Verification with a history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Design(rtl), perl, assertion based verification. knowledge in questa, cadence xcelium tool nd verdi.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC design and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 9 mos
Skills
- Universal Verification Methodology (uvm)
- Systemverilog
Career Highlights
- Expert in ASIC verification with UVM and SystemVerilog.
- Proficient in assertion-based verification methodologies.
- Strong background in digital design and verification.
Work Experience
Samsung Semiconductor
Staff Engineer (1 yr 4 mos)
MediaTek
Senior Engineer (2 yrs 5 mos)
asic verification (6 yrs 9 mos)
Education
Bachelor of Technology - BTech at GMR Institute of Technology (GMRIT), GMR Nagar, Rajam, Srikakulam Dt.,-532127 (CC-34))
Master of Science - MS at BITS Pilani Work Integrated Learning Programmes
Vlsi-front end design and verification at Maven silicon