Maheswari Durga Akula

Product Engineer

Iragavaram, Andhra Pradesh, India3 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in design verification engineering.
  • Proficient in SystemVerilog and UVM methodologies.
  • Strong educational background in Electrical Engineering.
Stackforce AI infers this person is a Design Verification Engineer with expertise in semiconductor and electronics industries.

Contact

Skills

Other Skills

SystemVerilogUniversal Verification Methodology (UVM)

Experience

3 yrs 10 mos
Total Experience
1 yr 4 mos
Average Tenure
3 yrs 5 mos
Current Experience

Amd

Senior Design Verification Engineer

Feb 2026Present · 2 mos

Analog devices

2 roles

Engineer, Design Verification Engineer

Promoted

Aug 2024Present · 1 yr 8 mos

Associate Engineer, Design Verification Engineering

Oct 2022Jul 2024 · 1 yr 9 mos

Uptycs

ELK (Elasticsearch, Logstash, and Kibana)

May 2022Oct 2022 · 5 mos · Greater Bengaluru Area

Education

National Institute of Technology, Andhra Pradesh

Bachelor of Technology - BTech

Aug 2018May 2022

Stackforce found 100+ more professionals with SystemVerilog & Universal Verification Methodology (UVM)

Explore similar profiles based on matching skills and experience