Sandeep Jana

Software Engineer

Bengaluru, Karnataka, India19 yrs 4 mos experience

Highly Stable

Key Highlights

20 years of experience in Pre-Silicon Front End Verification.
Expert in Design and Testbench Architecture.
Proficient in advanced verification methodologies and tools.

Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in SoC design and verification.

Contact

Skills

Other Skills

SystemCESLC++Platform IntegrationPlatform DesignVerilogTLMUnix Shell ScriptingPerl ScriptSystem VerificationARM ProcessorsModelingNCSimDebuggingAMBA AHB

About

I have 20 years experience in Pre-Silicon Front End Verification of Ip, Subsystems, Die, Multi Die etc. with proficiency in Design Architecture, Testbench Architecture, Verification Infrastructure, Methodology, HDL/HVL Language, Collateral development, Integration, implemented in multi-languages, targeted to achieve high quality (lesser bug escapes) Chip design and execution predictability. Apart from experience in defining Methodology for Verifying designs, I also have good experience of Tools & Flows used to compile and simulate the design, having driven adoption of many advanced technologies in projects.

Experience

19 yrs 4 mos

Total Experience

4 yrs 9 mos

Average Tenure

4 mos

Current Experience

Rivos inc.

Senior Member of Technical Staff

Nov 2022 – Dec 2025 · 3 yrs 1 mo · Bengaluru, Karnataka, India

Front End Verification of System on Chip

Intel corporation

Lead SOC Verification Engineer

Apr 2016 – Nov 2022 · 6 yrs 7 mos · Bengaluru Area, India

Stmicroelectronics

4 roles

Staff Engineer

Nov 2013 – Mar 2016 · 2 yrs 4 mos

Technical Lead

Promoted

Feb 2011 – Oct 2013 · 2 yrs 8 mos

As a Technical Lead I have following responsibilities:
> Leading TLM based verification activities at Greater Noida site.
> Central point of contact for managing TLM verification platforms for both IP and SOC level.
> Managing meetings, weeklies, customer interactions on weekly basis.
> Participate in technical discussions with the verification engineers for various projects.
> Being hyper active in resolving issues or problems faced by team mates in various verification activities.
> Make sure that none of the verification engineers are blocked in any project and provide them with my expertise to keep them unblocked.

Senior System Software Engineer

Promoted

Jan 2009 – Jan 2011 · 2 yrs

Design Engineer

May 2008 – Dec 2008 · 7 mos

Hcl technologies in vlsi group

Member Technical Staff

Jul 2006 – Apr 2008 · 1 yr 9 mos

During my tenure at HCL Technologies, I was mainly working at their customer site
CoWare (now Synopsys) in their services team on CoWare technologies and their
customer projects.
I also did 7 months training in HCL Technologies in the same VLSI department as part of
the requirement for my B Tech degree completion.