Jan 2022 – Nov 2022 · 10 mos

Dec 2016 – Dec 2021 · 5 yrs · Noida, Uttar Pradesh, India

• Lead Member of Consulting Staff in Testbench Express Team of Emulation Division
• Mainly working on Verilog Compiler.

Feb 2015 – Oct 2016 · 1 yr 8 mos · Bengaluru, Karnataka, India

• Started working in Formality front end R & D group.
• Current assignments are mainly bug fixes and enhancement in front end modules like
• vhdl/verilog parser
• IR for vhdl/verilog
• CDFG generation
• Synthesis
• Technologies used : C++,Lex & Yacc, Debugging tool GDB, Formality , DC , VCS, Perforce,Code Collaborator etc.

Jan 2012 – Jan 2015 · 3 yrs · Bengaluru, Karnataka, India

• Working on "Synphony C Compiler" Tool Development
• Feature enahancements and Bug fixes in frontend modules.
• Generate C part of testbench for a simulation model using UVM methodology
• Refactoring the modules with respect to parameter handling
• Dead Code , Scalarization , Struct handling etc
• Technolgies/tols used : C++, SUIF Compiler framework on linux platform, GDB , VCS , Perforce etc

Jun 2010 – Dec 2011 · 1 yr 6 mos · Bengaluru, Karnataka, India

• Working on "Synphony C Compiler" Tool Development.
• Feature enhancements and Bug fixes in front end modules.
• Suif IR
• Parameter handling
• Dead Code Elimination
• Scalarization
• Struct handling ....... etc
• Technolgies used : C++,SystemC,SUIF Compiler framework on linux platform, GDB ,Perforce etc

Jun 2005 – Jun 2010 · 5 yrs · Bangalore Urban, Karnataka, India

• Worked as a Senior Engineer in the Front team of High Level Synthesis Tool
• Mainly worked on feature enhancements and bug fixes in frontend modules.
• Genereate Bit Accurate/ Thread Accurate SystemC models from given C code.
• ROM/RAM referencing from C code
• Enhance all the modules to handle static variables.
• Bug fixes in classical compiler optimizations, dead code,scalarization,constant propagation etc
• Technologies used :C,C++, SystemC, SUIF compiler framework, GDB, CVS , VCS , Modelsim etc

Mar 2001 – May 2005 · 4 yrs 2 mos · Noida, Uttar Pradesh, India

• Worked as a Software Engineer in FPGA team.
• Mainly responsible for modeling the FPGA architecture in SystemC at a higher level of abstraction.
• Model the architecture and then map the real design on this model and siumulate
• Also did few project related to visualization of Timing Graph.
• Read the graph which is used for timing analysis and dump it in a format which is readable by VCG tool.
• Technologies used : C++ and SystemC on linux plateform, Rational tools like rational rose, clear case etc