May 2021 – Nov 2024 · 3 yrs 6 mos · Bengaluru, Karnataka, India

• Concept, Market/Competitive/Performance analysis, architecture for LLM on FPGA. oneAPI implementation of the same.
• GNN accelerator architecture for web-scale graphs.

Dec 2019 – Apr 2021 · 1 yr 4 mos · Bengaluru, Karnataka, India

• Enabling AI in Healthcare

Sep 2017 – Dec 2019 · 2 yrs 3 mos · Bengaluru Area, India

• Computer vision solutions for face analytics (recognition, age/gender/emotion classification, de-identification) and tracking. Detection and tracking algorithms enables various kinds of object counting in videos.

Jul 2015 – Aug 2017 · 2 yrs 1 mo

• Developed Architecture, Micro-architecture and lead team for deep learning solutions, computer vision(CNN, GEMM in particular)
• Architecture analysis of various CNN digital IPs to integrate into Intel SOC
• Developed Architecture for Natural Language Processing (NLP) for Intel server-FPGA.
• Part of an architecture team to develop a Machine Learning Engine
• Algorithms and POC for edge learning in Computer Vision and NLP clients
• Path Finding and algorithms for Genomics. Acceleration of PairHMM algorithm in the GATK pipeline.

Jul 2011 – Jul 2015 · 4 yrs

• Micro-architect and design lead of the MIPI Unipro (Phy layer in particular)
• Micro-architecture and design of a CNN (Convolutional Neural Network) IP

Apr 2010 – Jul 2011 · 1 yr 3 mos

• Prototyping and Validation of Cypress's Generation 4 Touch screen solution on FPGA. Responsible for porting digital IPs to FPGA, including creating models for those that cannot be ported directly onto the FPGA. A test-chip that interfaced to the touch screen, along with the FPGA was used to validate firmware and the digital design itself.

Jan 2008 – Apr 2010 · 2 yrs 3 mos

• Managed a team for H.264 high definition video encode. Responsible for Encoder architecture and RTL design/implementation of Intra mode decision. Also responsible for a C++ reference model for Integer Motion Estimation

Jan 2005 – Jan 2008 · 3 yrs

• Responsible for architecture, integration, validation of a multi-format high-definition video decoder. Primary contribution in H.264 format, which includes hardware software partitioning

Jan 2003 – Jan 2005 · 2 yrs

• Responsible for modifications to several DAA (Direct Access Arrangement) products from Silabs. Also worked on PLL and crystal oscillator analog designs

Jan 1999 – Jan 2002 · 3 yrs

• Training on CMOS digital and analog circuit design.
• Custom circuit design and layouts - includes a floating point adder and a micro-controller
• Layout design rule deck creation for various CMOS technologies