Parvinder Pal Singh

Software Engineer

Delhi, India15 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

9+ years in EDA/ESL domain
Expert in SystemC and TLM2.0
Proficient in ARM protocols and bus modeling

Stackforce AI infers this person is a highly skilled architect in EDA and ESL domains with a focus on performance modeling.

Contact

Skills

Core Skills

Tlm2.0Systemc

Other Skills

AXIACECHIDevice DriversEmbedded SystemsEDAFunctional VerificationEmbedded LinuxSoCVLSIRTOSAlgorithmsSimulationsC

About

Having 9+ years of work experience in the EDA/ESL domain. Having experience of creating performance models for architecture exploration use case using SystemC and TLM2.0. Worked on creating various modules from scratch which includes writing down specification to the production of the module for architecture exploration use cases. Good knowledge of various coherency protocols handling coherent interconnect and different level of cache controller blocks. Created various transactor for the different protocol at various abstraction level for different use cases like Co-simulation, performance exploration, and functional verification Worked on creating Functional model for software validation use case using SystemC and TLM2.0 Specialties: Bus modeling with TLM2.0, Interconnect, SystemC, Knowledge of ARM FM Bus Protocols: AXI4, AXI3 ACE-Lite, ACE, CHIB, and C, APB Tools: Synopsys PA tools for architecture exploration (PA-MCO), VPA (for virtual platforms), TLMC, Virtualizer Studio Scripting Languages: TCL, Perl Languages: C, C++, SystemC, TLM2.0, Also have some basic knowledge of the hardware language (VHDL/Verilog).

Experience

15 yrs 3 mos

Total Experience

4 yrs 1 mo

Average Tenure

12 yrs 11 mos

Current Experience

Nvidia

Sr Architect

Nov 2021 – Present · 4 yrs 5 mos · Bengaluru, Karnataka, India

Synopsys inc

4 roles

Sr R&D Engineer 2

Jun 2018 – Oct 2021 · 3 yrs 4 mos

Sr. Member of Technical Team

Promoted

Jun 2015 – Present · 10 yrs 10 mos

Here I am involved on various solutions to explore performance of your system. I am also involved in developing some Generic IP to explore performance of your system.

Sr. RnD Engineer

May 2013 – Jun 2022 · 9 yrs 1 mo

R & D engineer level2

May 2013 – Jun 2015 · 2 yrs 1 mo

Working as a R&D engineer at synopsys india, here I have worked on various Transactors that convert like FT AXI (extension on TLM) to Pin Accurate level, also from CHI AT level to CHI Pin Accurate. I have gained good knowledge of AXI, ACE, CHI protocol of ARM and modeling them using TLM2.0 and SystemC

AXIACECHITLM2.0SystemC

Circuitsutra

3 roles

Member of Technical Staff

Jul 2012 – Apr 2013 · 9 mos

Creating functional model of the devices. Guiding juniors, there I was managing team of 2 person.

SoC Modelling Engineer

Nov 2010 – Jun 2012 · 1 yr 7 mos

Working experience on SystemC and TLM2.0. Developed TI specific BUS using TLM and added a convenience layer over it. Currently working for TI on client basis and handling development of IP model and support for cache coherency as per ARM protocol, Modelling at various abstraction level

SystemCTLM2.0

SoC Modelling Engineer

Nov 2010 – Jun 2012 · 1 yr 7 mos

On Client basis in Texas Instrument
CBA over TLM at CircuitSutra
Test suit for Synthesizable subset at Circuit sutra
Ramp Up at Circuitsutra
Sudoku Solver at DKOP
ADHOC network at ERNET india
op-amp IC during b.tech
Contact management System during b.tech
Description
Here I have designed some TI specific IP on Fast Models. Supporting Arm FM. Have also performed the cache coherency management between ARM and IP of TI.
In this project I have created CBA architecture of TI using TLM that can be used at three abstractions level (cycle accurate, approximate timed and Loosely timed). Also I worked on Various adaptor that will convert Base TLM to CBA and vice versa.
In this project I have created test cases in SystemC that is to be synthesized in Verilog code using Cadence CtoS.
I am also involved in ramp up of new joined on SystemC and TLM-2.0
Using TCl tool language I created Sudoku solver module.
Worked on encryption and decryption algorithm of ADHOK network using Java Language.
Designing of two stage op-amp IC in VLSI using cadence tools(CHIP DESIGNING)
Design contact management system for organization using JAVA language; ISCUG
I am active participant on OSCI and have solved queries asked by many person related to SystemC and TLM. Also Pointed out BUGS in the Simulator(POC) provided by OSCI and that has been accepted too.
I have also Presented about Convenience layer built over TLM2.0 in ISCUG 2012