Dec 2023 – Jun 2025 · 1 yr 6 mos · Noida, Uttar Pradesh, India · Hybrid

• Contributed to Architectural Exploration of high-performance SoCs for custom silicon targeting AI/ML and large language model (LLM) workloads—spanning both training and inference use cases. Focused on developing cycle accurate performance models(AT) and virtual prototypes to guide early architectural decisions for next-generation compute platforms.
• Key Responsibilities:
• Led SoC architecture modeling and performance analysis using SystemC and TLM 2.0 for AI accelerators, LLM inference chips, and multi-die training architectures.
• Developed high-fidelity virtual models for DDR5/6, LPDDR5/6, HBM3/4 memory controllers, system interconnects (AXI, CHI, NoC), and SMMUs.
• Drove platform-level performance benchmarking using Synopsys Platform Architect to evaluate throughput, memory bandwidth, and latency under AI/ML and LLM workloads.
• Enabled rapid design space exploration and architectural trade-off analysis (PPA) for data movement, compute/memory balance, and interconnect efficiency.
• Collaborated closely with SoC architects, and RTL/IP teams to enable first-pass success of AI-centric silicon.
• Proficiency in C/C++, SystemC, TLM2.0, Data Structures and Algorithms, Embedded Systems, Computer Architecture, Virtual Prototyping, Hardware Modeling and exposure to SystemVerilog.
• Awards & Publications:
• Optimizing HBM Memory in Multi-Die Systems – IEEE
• High-Bandwidth Memory (HBM) in Custom Compute Systems: An Architectural Exploration for future Computing Pardigm - DVCon25
• Design Space Exploration of SMMU – EILC
• Individual Excellence Award – Generic SMMU Model
• Spotlight and Special Recognition – Designware SNPS LPDDR5 and HBM3 Controller Contributions

Mar 2022 – Dec 2023 · 1 yr 9 mos · Noida, Uttar Pradesh, India · Hybrid

• Key Responsibilities:
• Led architecture exploration for AI-focused SoCs, optimizing memory subsystems and interconnects for data center compute platforms.
• Analyzed performance using Synopsys Platform Architect to optimize data movement across SoC fabrics.
• Developed SystemC TLM 2.0 models for fast prototyping and collaborated with software teams for early validation.

Dec 2020 – Nov 2021 · 11 mos · Pune Division, Maharashtra, India · Hybrid

• Contributed to the development of core analytical engines powering Cytel’s Solara—a simulation-based platform for data-driven decision-making in clinical trial design. These engines enable the generation and evaluation of artificial trial data across a wide range of statistical scenarios, significantly accelerating drug development strategies.
• Key Responsibilities:
• Collaborated with team of eight to implement a C++ analytical engine to carry out Difference of Mean, Difference of Proportion hypothesis tests for Superiority and non inferiority designs in case of Phase III clinical trials.
• Optimized the computation time using Statistical Algorithms and STL in C++ along with OpenMP.
• Employed tree and graph data structures with multi threading in C++ by creating a software module to improved performance of existing C++ engines.
• Contributed to Statistical computation engines while introducing algorithms such as simulated Annealing (a probabilistic technique for approximating the global optimum) in order to reduce overall simulation time.

Jan 2019 – Nov 2020 · 1 yr 10 mos · Vadodara, Gujarat, India · On-site

May 2018 – Jul 2018 · 2 mos · Jaipur, Rajasthan, India

• Relevant Coursework: Networking & Security