Apr 2024 – Jul 2025 · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

• High Performance Out-Of-Order Lead
• Leading the PD convergence of all the blocks in High Performance P Series Cores
• Driving RTL analysis, performance trade-offs and enhancements related to PPA
• Developing hierarchical flows & budgeting methodology

Jun 2022 – Mar 2024 · 1 yr 9 mos · Bengaluru, Karnataka, India · On-site

• Part of RISC-V High Performance Out-Of-Order CPU Cores Team
• Involved in PD convergence & RTL feasibility, targeting High Frequency & Area targets in TSMC N3 nodes.
• Load-Store Unit PD
• Owning PD convergence of Load-Store Unit from synthesis to GDSII, most complex CPU block w.r.t. architecture, and PPA
• Critical PPA improvements related to congestion, skewing, and place-to-route timing jump
• Load-Store Unit RTL
• Working with uArch designers & performance teams to ideate and improve the RTL
• Creating schematics & analyzing high logic depth paths. Checked in a few RTL timing fixes as well
• Logical ECOs & Formal Verification
• Developed flows for FEV in case of retiming & ungrouping enabled designs
• Responsible for Manual/automated ECO creation & verification across projects
• Created manual ECOs for a wearable tapeout design, resulting in <10% new gates compared to automated ECOs
• CLP
• Built hierarchical UPF designs, and helped define PG spec for future projects
• Worked with CAD to develop FC flow for multi power domains and voltage area

Oct 2020 – Jun 2022 · 1 yr 8 mos · Bengaluru, Karnataka, India

• Part of CPU Core Physical Design Team for Google Tensor SOCs
• Involved in block PPA convergence (from synthesis to ECOs) & IR Convergence
• Floating Point Unit PD (ARM X1 Core)
• PD Convergence of Floating Point Unit, targeting 3 GHz in Samsung 4nm node
• Drove discussions with ARM to improve the bounds & module placement
• Achieved better frequency and power-iso-perf curve over target
• IR Convergence
• Owned the EM and IR convergence for the core, using innovative techniques for IR closure
• Evaluated Tweaker ECOs and PGFill for IR convergence, converting it to flows that can be used for all IPs
• Partitioning & PPA Improvements
• Owned the regular top-level DEF Pushdowns for all the blocks based on various constraints
• Drove discussions with the EDA vendor for tool issues and enhancements, targeting skewing & powerOpt which helped improve multiple IPs
• Developed scripts for Latency Locking to improve clock skewing and reduce run-to-run variations
• Wearable SoC PD
• Owned the complete PD Execution of always-on and application cores, with target of leakage minimization
• Evaluated different ARM cores considering PPA Targets. Worked with architects for reviewing the CPU options such as FP+Neon, crypto logic, and cache size.

Jun 2018 – Oct 2020 · 2 yrs 4 mos · Bengaluru, Karnataka, India

• Was a part of the Image Processing Unit and Graphics LLC Teams
• Worked on block PPA optimization for 4 different tape-ins from Synthesis to GDSII, including ECO DRC & Timing convergence
• Worked as a section timing owner, analyzing section-level STA and generating timing ECOs
• PVC (TSV connected 3D Graphics Die) LLC
• PPA optimization of a partition with congestion challenges
• DoP (drop-off points) modeling to minimize clock skew and fix clock transition violations
• Placement and timing constraints for high RP units in multi-voltage design
• Intel Discrete Graphics
• Converged timing-critical cross-section paths and dual data rate paths with high cross-talk delta
• Automated flop duplication for critical timing paths
• IPU (Image Processing Unit) Team
• Worked on MMU & Noise Reduction blocks