Dec 2020 – Jan 2025 · 4 yrs 1 mo

• Leading CPU synthesis team for few projects. Responsibilities include synthesis, constraints development & validation, pre-layout STA, formal verification, low power static checks.
• Leading CPU power for few projects. Responsibilities include defining dynamic & leakage power targets, execution of PTPX runs, analysis, feedback & tracking. Post-Si support for correlation.

Jan 2017 – Nov 2020 · 3 yrs 10 mos

• Worked in CPU Implementation team on synthesis, constraints, pre-layout STA, formal verification, low power static checks.
• Also worked on low power analysis (dynamic & leakage power calc, analysis & optimization/feedback) on impl side.

Jul 2012 – Dec 2016 · 4 yrs 5 mos

• Owned & executed constraint development, management, SDC generation & timing analysis at pre-PD stage for multi-million GNB sub-system (at block & top level).
• Worked on DFP for latest low power chips which included UPF generation, static low power checks at block & full chip level.

Oct 2009 – Jun 2012 · 2 yrs 8 mos

• Owned Implementation steps for some blocks which included RTL lint, synthesis, formal verification & timing.
• Completely owned below for GNB sub-system
• Repeater flow - AMD flow to meet timing at full chip level between blocks in huge & complex hierachical SoC designs by adding pipeline stages.
• Constraints flow - Constraint organization & development at SoC level interacting will multiple IPs & finally driving towards STA closure
• Gained experience with multiple technology nodes (40nm & 28nm) & foundaries during this period.
• Also, concurrently mentored new college graduates as part of my personal / leadership development goals.

Apr 2008 – Sep 2009 · 1 yr 5 mos

• Executed PnR for 2 blocks of 400K instances each from floorplaning, placement, CTS, SI aware routing & timing closure to DRC fixing.
• Involved in budgeting of full chip SDC (>100M instances) to block level, analyzing & providing feedback on timing issues etc.

Jun 2005 – Mar 2008 · 2 yrs 9 mos

• Worked on RTL analysis (mainly for DFT coverage), Synthesis, STA & formal verification at full chip level. Basic exposure to DFT.

Jul 2004 – Dec 2004 · 5 mos

• Developed methods for improving design (Verilog Netlist) simulation/verification speed. Could achieve upto 30% improvement in speed with different techniques employed with some acceptable limitations.