Atul Negi

Software Engineer

Noida, Uttar Pradesh, India12 yrs 9 mos experience
Highly Stable

Key Highlights

  • 10+ years in Verification IP development
  • Expert in UVM and System Verilog
  • Strong problem-solving and analytical skills
Stackforce AI infers this person is a Verification Engineer in the semiconductor industry.

Contact

Skills

Core Skills

System VerilogUvm

Other Skills

UVM MethodologyMicrosoft ExcelHTMLPowerPointMicrosoft WordEnglishVCS

About

10+ years of Industry experience in Verification IP development. Strong problem solving and analytical skills. A good team Player Expertise: UVM, System Verilog, Verilog, Simulation VIP BFM development

Experience

12 yrs 9 mos
Total Experience
5 yrs 8 mos
Average Tenure
1 yr 5 mos
Current Experience

Amd

Senior Member of Technical Staff

Dec 2024Present · 1 yr 5 mos · Bengaluru, Karnataka, India · Hybrid

  • GFX Team

Cadence design systems

2 roles

Sr Principal Design Engineer

Jul 2024Nov 2024 · 4 mos · Hybrid

System VerilogUVM MethodologyUVM

Principal Design Engineer

Apr 2022Jul 2024 · 2 yrs 3 mos · Hybrid

  • Verification of TCL Script Used to Generate Register Values
  • June'2022 – Oct 2022
  • Enhanced testbench to verify customer deliverable scripts for default register settings.
  • LPDDR5 WCK Free Running Mode
  • Dec'2022 – Jan 2023
  • Updated TB components to verify LPDDR5 WCK free running mode feature.
  • INIT/DFS Support in Behavioral PHY Model
  • Feb'2023 – July 2023
  • Developed INIT and DFS support for DDR5, LPDDR4, and LPDDR5 protocols.
  • AXI 5 Poison
  • Aug'2023 – Dec 2023
  • Updated TB to verify AXI5 poison feature support in controllers.
  • Test Bench Infra Project
  • Jan'2024 – Till Date
  • Enhanced existing TB for handling randomization of variables and handling various methods for multiple DDR protocols.
System VerilogUVM MethodologyUVM

Synopsys inc

4 roles

Sr R&D Enginner II

Jun 2020Apr 2022 · 1 yr 10 mos

  • Ethernet Transactor Development and Verification
  • June'2020 – April 2021
  • Enhanced Ethernet transactor with additional features like FEC, FlexE 2.0, and hardware to software message interfaces.
  • Development of 800G Ethernet Verification IP

Sr R&D Engineer I

Sep 2017Jun 2020 · 2 yrs 9 mos

  • 1) Ethernet VIP
  • 1G BaseT1 IEEE 802.3bp
  • FLexE

R&D Engineer II

Jul 2015Sep 2017 · 2 yrs 2 mos

  • 1) MLG-OIF 2.0 (Multi Link Gearbox)
  • 2) Ethernet VIP Development- specification from IEEE 802.3
  • 200G Base-R PCS IEEE 802.3bs
  • 400G Base-R PCS IEEE 802.3bs
  • 25G IEEE 802.3by
  • PAM4 and PAM4 Test Patterns
  • 3) BOSCH CAN VIP
  • CAN 2.0 Part A and Part B
  • CAN FD
  • CAN TT

R&D Engineer I

Jun 2013Jun 2015 · 2 yrs

  • 1) Ethernet VIP Development- specification from IEEE 802.3
  • 10 Gbps
  • 20 Gbps
  • 40 Gbps
  • 100 Gbps
  • 25 Gpbs/50 Gbps Consortium draft:
  • a. Without FEC
  • b. With clause 74 FEC.
  • c. With Clause 91 RS-FEC
  • 2) Fibre Channel VIP Development
  • 16 Gbps
  • 32 Gbps
  • Speed Negotiation

Education

Delhi College of Engineering

Bachelor of Engineering (B.E.) — Electronics and Communications Engineering

Jan 2009Jan 2013

Stackforce found 100+ more professionals with System Verilog & Uvm

Explore similar profiles based on matching skills and experience