Anuj Pandey

Software Engineer

Bengaluru, Karnataka, India13 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced Staff Engineer with expertise in RTL design.
  • Proficient in multiple hardware description languages.
  • Strong background in ASIC design and verification.
Stackforce AI infers this person is a Hardware Design Engineer with a focus on ASIC and RTL methodologies.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignAsic

Other Skills

CVerilogSystem VerilogUVMAMBA AHBAMBA AXIAMBA APBSVAJavaHTMLJavaScript

Experience

13 yrs 3 mos
Total Experience
4 yrs 5 mos
Average Tenure
5 yrs 7 mos
Current Experience

Qualcomm

2 roles

Staff Engineer

Dec 2022 – Present · 3 yrs 4 mos

Sr. Lead Engineer

Aug 2020 – Nov 2022 · 2 yrs 3 mos

L&t technology services limited

Sr. Engineer

Aug 2016 – Jul 2020 · 3 yrs 11 mos

Techvulcan solution pvt. ltd.

Associate Engineer

Oct 2012 – Jul 2016 · 3 yrs 9 mos · Bengaluru Area, India

  • Design and verification engineer.
  • Languages - C, Verilog, System Verilog
  • Methodology - UVM
CVerilogSystem VerilogUVMRTL designASIC

Education

Echelon institute of technology

Bachelor of Technology (B.Tech.) — Electronics and communication Engineering

Jan 2007 – Jan 2011

k.l.Mehta Dayanand Public school

12th

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