Swetha Gunda

Director of Engineering

Bengaluru, Karnataka, India18 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 10 years in physical design flow.
  • Led teams of 65+ for IP block signoff.
  • Expertise in static timing analysis and closure.
Stackforce AI infers this person is a Semiconductor Engineering Leader with extensive experience in physical design and timing analysis.

Contact

Skills

Other Skills

Static Timing AnalysisTiming ClosurePhysical DesignVLSIASICSoCDRCLVSPrimetimeEDAClock Tree Synthesis

About

Have 10+ years of experience in Physical design flow from Netlist to GDS11, on latest technologies. Also has experience with STA in block level and Chip level closure.

Experience

18 yrs 6 mos
Total Experience
4 yrs 7 mos
Average Tenure
6 yrs 4 mos
Current Experience

Amd

2 roles

Senior Technical Manager

Promoted

Jul 2025Present · 9 mos · Hyderabad, Telangana, India

Physical Design Manager

Dec 2019Jul 2025 · 5 yrs 7 mos · Hyderabad, Telangana, India

Synapse design inc.

Senior Technical Lead

Mar 2018Dec 2019 · 1 yr 9 mos · Bangalore

  • Responsible for Multiple IP blocks implementation for physcial design flow to tapeout.
  • Was leading 65+ people owning 120+ blocks for signoff closure.

Amd

MTS Design Engineer

Jun 2011Feb 2018 · 6 yrs 8 mos · Greater Hyderabad Area

  • Owning blocks for tapeout through complete PD flow as a lead/individual owner. Also works for Fullchip for timing closure.
  • Also worked as IP lead, for high frequency IP, leading 30+ blocks to tapeout.

Soctronics

Sr P & R engineer

Aug 2007May 2011 · 3 yrs 9 mos

  • Running the tiles through PD flow for tapeout.

Education

VEDA IIT

M.Tech — VLSI

Jan 2006Jan 2008

Bapatla Engineering College

Bachelor of Technology (B.Tech.)

Jan 2001Jan 2005

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