Rishabh Puri

Software Engineer

Bengaluru, Karnataka, India10 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI and Digital Circuit Design
Proven track record in semiconductor projects
Strong leadership and management skills

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and digital circuit design.

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Skills

Core Skills

Digital Circuit DesignVlsiCircuit DesignHardware Description Language

Other Skills

CC++VerilogStatic Timing AnalysisMonte Carlo simulationCadence VirtuosoTiming analysisPower analysisLatch analysisImpact analysisLeakage analysisTiming closureLTSpiceLinuxShell scripting

Experience

10 yrs

Total Experience

3 yrs 3 mos

Average Tenure

5 yrs 5 mos

Current Experience

Intel corporation

Digital Design Engineer

Nov 2020 – Present · 5 yrs 5 mos · Bengaluru, Karnataka, India

Working on advanced intel CPU core design and enabling layout as well PDE team .
1.10nm intel Finfet technology . Multiple stepping for timing as well as power convergence .
2. 7nm intel Finfent technology .

CC++VerilogVLSIDigital Circuit DesignStatic Timing Analysis

Stmicroelectronics

Circuit Design Engineer

Dec 2017 – Nov 2020 · 2 yrs 11 mos · Noida, Uttar Pradesh, India

Project -QUINTPORT (5 port (4Read & 1Write) compiler development banking structure ) for Space application
> RNM,WM bitcell analysis using Monte Carlo simulation.
>Design of Local Control , LIO and Dummy rowdec in virtuoso from scratch.
> Sizing & Standalone simulations of design block.
>Resistance and capacitance calculations implementation in prelayout and check with the layout team .
>Intermediate timing power (setup hold cycle and dynamic power)calculations on Prelayout .
>XTALK analysis for GLOBAL and LOCAL bitlines and make them isolated .
>RD selftime with marginality (Discharging and NonDischarging Case)
>Glitch analysis
>Latch analysis
>Monte carlo simulation for Self Time.
>PostLayout extraction analysis and Plugin .
>CCF(Cad Correction Factor) implementation .
>Submission and Signoff
Project - SPHD- C40 platform
>Timing closure with impact analysis.
>power analysis(dynamic and standby)
>marginality analysis with variation due to spice and silicon change .
>redundancy margins
>make architecture INITIN free (reset pin free)
>signoff closure
Project- DPHD-28-SOI for samsung
>CPTS(Critical path tight Stimuli)
>Latch Analysis
>Impact Analysis(spice impact and redundancy latch)
>ESPCV
Project - ROM_28_FDSOI
work - latch analysis by calculating leakage and checking the robustness of the circuit
>impact analysis after the design changes from 32nm to 28nm
>scan chain effect
>espcv
>margins and timing closure

VerilogMonte Carlo simulationCadence VirtuosoTiming analysisPower analysisCircuit Design+1

Zia semiconductor pvt ltd

Design Engineer

Jul 2017 – Nov 2020 · 3 yrs 4 mos · Bangaon, West Bengal, India

working as circuit designer . working on ltspice creating netlist , perl and shell scripting, linux , clock generator circuit.
bitcell characterization
sense characterization
timing analysis
setting margins
designing memory circuit finfet on 40nm,14nm.
layout memory design finfet in 40nm , 14nm ,10nm.

LTSpiceLinuxShell scriptingClock generator circuit designCircuit Design