Jul 2021 – Present · 4 yrs 10 mos · On-site

• Network Edge Client SoC - Functional Security Validation (Apr '24 to Present)
• Leading a team of four to drive security functional validation on an Intel Client SoC.
• Developed FIPS 140-3 validation strategy for random number generator to ensure technical readiness of the product.
• Established a Security Workgroup to enhance knowledge sharing on security modules among team members.
• Created comprehensive test plans by reviewing those from the parent product.
• Executed test cases on the N-1 platform to ensure power-on readiness and stability.
• Network Edge Server SoC - Functional Security Validation (Apr '21 - Mar '24)
• Led a team of four in validating security functionalities on Intel Xeon Scalable processors with VRAN boost.
• Created test plans, adapted and developed test cases for Intel server-based security features.
• Validated security features including Secure Boot (Boot Guard, Bios Guard, TXT), Chassis Security, Memory Encryption (TME, MKTME), Confidential Compute (SGX &TDX).
• Collaborated with the manufacturing team to ensure proper fusing for enabling security technologies.
• Used the N-1 platform for legacy feature validation and an emulation vehicle for testing new features for power-on readiness.
• Conducted volume validation, debugged key issues during validation failures, and filed bugs to ensure robust security.

Jul 2017 – Jun 2021 · 3 yrs 11 mos · On-site

• Deep Learning Accelerator SoC - Security, Fuse, and Neural Processing Unit (NPU) Validation (Jun '19 - Mar '21)
• Led the development of assertions for ROM code validation, ensuring correct sequencing of signals required for NPU power-up.
• Ported and executed NPU test cases from IP level to SoC on emulation, debugging and validating them effectively.
• Directed pre-silicon verification and post-silicon validation of Security and Fuse IPs at the SoC level.
• Designed comprehensive test plans, testbenches, and test cases for ARM Cortex-A55 and Cortex-A53 based security architecture; conducted TSMC 7nm eFuse verification.
• Validated key security features, including interconnect-based firewalls, DFX security features, crypto modules, and random number generators; ensured robust eFuse security and controller features.
• Achieved design maturity through extensive functional and security coverage, conducting waveform reviews with architects and designers to improve verification quality and ensure a bug-free design.
• 5G Modem SoC - Security and Fuse Validation (Jul '17 - May '19)
• Led pre-silicon verification and post-silicon validation of Security and Fuse IPs at the SoC level.
• Developed test plans, testbenches, and test cases for ARM Cortex-R8 and Cortex-A53 security architecture; conducted TSMC 7nm and Intel 14nm eFuse verification.
• Validated a range of security features, including register lock features, access control firewalls, DFX security features, crypto modules, and random number generators.
• Ensured design maturity through comprehensive functional and security coverage, conducting waveform reviews with architects and designers to maintain high verification quality.
• Enabled test content on emulation vehicles for power readiness, collaborating with the post-silicon team to ensure seamless power-on and validation processes.
• Silicon bringup, debug and scenarios replication in presilicon environment, Security development lifecycle signoff

Jan 2017 – Jun 2017 · 5 mos · On-site

• 4G based wearable SoC - (Jan'17 - Jun'17)
• Responsible for functional validation of clock generation unit in 4G wearable SoC
• Test plan creation, test content development and test execution on IP level and SoC level RTL simulations
• Development of checkers through System Verilog assertions to measure clock frequencies.
• Assertion automation framework for validation of system power control units FSMs.
• All the above activities ensured a smooth power on and a bug free clock IP on silicon.