Narasimharao Devineni

CTO

Bengaluru, Karnataka, India19 yrs 8 mos experience

Highly Stable

Key Highlights

19+ years in IP design and NAND flash controller designs.
Expertise in LPDDR controllers and DDRPHY designs.
Proven leadership in RTL design and micro-architecture.

Stackforce AI infers this person is a semiconductor design expert with a focus on memory controller architecture.

Contact

Skills

Core Skills

Rtl DesignMemory Controller DesignDdr Phy DesignAsic DesignTechnical LeadershipIp DesignMicro-architecture

Other Skills

Logic DesignVerilogSystemVerilogLow-power DesignDDR PHYSilicon ValidationASICTechnical DesignMemory CardsIntegrationPost Silicon validationSoCHDMISiliconIntel

About

Total of 19+ years of Industry experience in delivering IP design / IP subsystems / NAND flash controller designs. A total of 7+ years of experience in LPDDR controllers & DDRPHY designs. Currently as RTL Design Lead for LPDDR5x & LPDDR6 Memory controller design. Experience in leading an IP Design team for micro-architecture definition & RTL design implementation from an industry latest evolving LPDDR6 JEDEC spec for Perf-Power-Area optimizations.

Experience

19 yrs 8 mos

Total Experience

5 yrs 5 mos

Average Tenure

3 yrs 4 mos

Current Experience

Google

ASIC RTL Design Lead

Dec 2022 – Present · 3 yrs 4 mos · Bengaluru, Karnataka, India · On-site

LPDDR6 Memory Controller design Lead

Logic DesignRTL designVerilogSystemVerilogLow-power DesignMemory Controller Design

Qualcomm

Senior Staff Engineer

Nov 2018 – Dec 2022 · 4 yrs 1 mo · Bengaluru Area, India

DDR PHY Frontend design lead for Qualcomm's snapdragon platforms

DDR PHYRTL designSilicon ValidationDDR PHY Design

Western digital

Technologist

Jan 2017 – Nov 2018 · 1 yr 10 mos · Bengaluru Area, India

ASIC Controller technical design lead for Western Digital's next generation SD 6.0 memory cards

ASICTechnical DesignMemory CardsASIC DesignTechnical Leadership

Intel

2 roles

Senior RTL Design Engineer

Promoted

Jan 2010 – Dec 2016 · 6 yrs 11 mos · Bangalore

I've extensively worked on integration IP/sub-block designs into IP subsystems. Also have experience in developing scalable IP designs, successfully developed the micro-architecture for Interconnect fabric designs for IP subsystems, scalable memory controller design & micro architecture of sub-blocks in IP design & worked on low power features of IP.
I've demonstrated strong RTL design skills in Verilog/System Verilog for IP blocks from which are coded from scratch. I've good experience in performing complex Engineering Change Order (ECO) for late design bugs

IntegrationMicro-architectureLow-power DesignIP Design