Robin John

CTO

Bengaluru, Karnataka, India12 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 12 years of experience in ASIC and SoC integration.
  • Expert in Verilog/System Verilog and RTL integration.
  • Proven leadership in cross-functional team management.
Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in ASIC and SoC design and integration.

Contact

Skills

Core Skills

Rtl DesignTeam LeadershipSystem On A Chip (soc)Rtl IntegrationStatic Timing AnalysisAxiDigital LogicMipi Dphy

Other Skills

MIPI CSI2Unified Power Format (UPF)ScriptingASICTeamworkCross-functional Team LeadershipStratusCDCSystemCHBMDDR4DisplayDebugging circuit boardMIPI DSIDebugging Code

About

Engineering leader with ~12 years’ experience in ARM-based full chip SoC integration, image/video ASIC IP design and integration, and FPGA. Proven in leading crossfunctional teams, managing full ASIC lifecycles, and optimizing FPGA flows for early SW/FW validation. Expert in Verilog/System Verilog and RTL integration, focused on scalable methodologies, performance optimization, and mentoring teams to deliver high-quality, on time results.

Experience

12 yrs
Total Experience
4 yrs
Average Tenure
6 yrs 4 mos
Current Experience

Intel corporation

5 roles

Engineering Leader – ASIC • SOC• FPGA

Promoted

Sep 2025Present · 8 mos

Engineering Manager

Promoted

Oct 2024Sep 2025 · 11 mos

FullChip SoC Integration Lead

Jan 2023Aug 2024 · 1 yr 7 mos

  • Experienced in integrating 21-partition SoCs with ARM A53 processors and complex NoC bus architectures. Led the entire SoC integration process, including LEC, LINT, FC elaboration checks, MBIST and CSM insertion for scan, and CDC/RDC analysis, delivering top-quality designs to the PD/DFT team.
ScriptingRTL integrationSystem on a Chip (SoC)Unified Power Format (UPF)ASICTeamwork+2

ASIC Design and Integration Team lead

Jul 2022Sep 2024 · 2 yrs 2 mos

  • Experienced in managing the micro-architecture specification, RTL/SystemC implementation, and integration of Image Processor IPs. Successfully led a high-impact front-end team of three members, ensuring timely completion of their deliverables.
MIPI DPHYMIPI CSI2RTL DesignUnified Power Format (UPF)Team LeadershipStatic Timing Analysis+1

Graphics Hardware Engineer (ASIC IP Logic Design )

Nov 2019Jun 2022 · 2 yrs 7 mos

  • IPU integration, CDC, Lint.
  • Imaging Algo Design using High Level Synthesis.
  • RTL Design.
StratusRTL integrationRTL DesignCDCStatic Timing AnalysisDigital Logic+1

Xilinx

Design Engineer II

Sep 2017Nov 2019 · 2 yrs 2 mos · Hyderabad Area, India

  • AXI Stream Master RTL design.
  • HBM/DDR4 performance Validation on Hardware.
HBMDDR4Digital LogicAXI

Lattice semiconductor

Application and Solution Engineer

Mar 2014Aug 2017 · 3 yrs 5 mos · Hyderabad Area, India

  • RTL Design of MIPI CSI2/DSI Tx/Rx Micro blocks.
  • Initially hardware board bring up.
  • Demo design with camera & Displays for MIPI CSI2/DSI reference design.
  • PCIE DEMO Design & Hardware bring up.
MIPI DPHYDisplayMIPI CSI2Debugging circuit boardMIPI DSIDebugging Code+2

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — MicroELectronics

Centre for Development of Advanced Computing (C-DAC)

Postgraduation Diploma - Advance VLSI Design — VLSI

Kendriya Vidyalaya

Physics Chemistry Math

Lovely Professional University

Bachelor of Technology (BTech) — ECE

Stackforce found 100+ more professionals with Rtl Design & Team Leadership

Explore similar profiles based on matching skills and experience