Sai Charan Reddy — Software Engineer
Experienced design engineer covering RTL Coding for FPGA, RTL checklist (Lint, CDC, Code coverage and Synthesis). Knowledge on UVM , assertions, functional coverage. Deep knowledge on PCIE Gen6 phy layer, PCIE Gen6 retimer, PIPE SERDES interface, AXI4 , AXI stream, UART, Wishbone, SPI and JESD 204B protocols. Exposure on TCL, Shell , Python.
Stackforce AI infers this person is a highly skilled RTL design engineer specializing in FPGA and PCIe technologies.
Location: Chittoor, Andhra Pradesh, India
Experience: 5 yrs 9 mos
Skills
- Rtl Development
- Pcie
- Static Timing Analysis
- Vhdl
Career Highlights
- Expertise in RTL design and FPGA coding.
- Deep knowledge of PCIe Gen6 and related protocols.
- Proficient in multiple hardware description languages.
Work Experience
Logic Fruit Technologies
Senior Lead Engineer (1 yr 10 mos)
Module Lead (2 yrs 1 mo)
Research And Development Engineer (1 yr 9 mos)
R&D trainee (5 mos)
Education
BTech - Bachelor of Technology at National Institute of Technology , Patna
