Meenal Kudalkar — Director of Engineering

- Highly enthusiastic, self-driven and self-motivated, confident leader in RTL design, architecture, and verification support of leading edge products in HDD, SSD, and networking domains - 23 years of extensive experience mainly in VLSI ASIC design domain presently working at Intel Bangalore for past 4.5 years - Technical Sr. design manager with 10+ years of experience in management with extensive experience in FE development of HDD/SSD controller SoCs, Vision family of products in client segment, AI ML based POC IPs - Expertise in technically managing SoC FE design development as well as complex IP design development - In past, have technically lead and worked hands-on on complex IP design development in HDD/SSD as well as Networking domain - Extensive experience in supporting post silicon chip validation from design standpoint - Very good experience in supporting implementation and physical design teams from design standpoint in implementation flow all the way to chip tapeout - Good understanding of chip development flow all the way from defining product specifications to post silicon validation - Have contributed to and delivered multiple first pass silicon - Experienced in managing and collaborating across multi-geographical teams - Close interaction with verification, validation, physical implementation, and FW teams - Hands-on experience in RTL design, gate level simulations, sandbox verification, structural checks, CDC and lint, power and die estimation, power and voltage domain architecture, ROM and memory generation, ROM simulation support, floor-planning guidance - Transparent work culture, believes in the team effort and in trust in the team for success

Stackforce AI infers this person is a leader in VLSI ASIC design and SoC development.

Location: Bengaluru, Karnataka, India

Experience: 26 yrs 4 mos