Sivasankar Reddy — Software Engineer
Strong Knowledge in Digital Electronics and verilog. Knowledge on System Verilog and UVM. Experience with setting up GLS environment and running gate level simulations. Debugging the gate level simulations in subsystem level and soc level with zero delay and timing(SDF). Experience in constraint randomization and functional coverage features in verification environment. Knowledge on bus protocols like AMBA AHB-APB, AXI. Experienced in developing new test cases and debugging failing test cases working experience with synopsys tools like vcs, Verdi
Stackforce AI infers this person is a Verification Engineer in the Semiconductor industry.
Location: Kandukur, Andhra Pradesh, India
Experience: 7 yrs 8 mos
Skills
- Verification Engineering
- Digital Electronics
Career Highlights
- Expert in Digital Electronics and Verification Engineering.
- Proficient in Verilog, System Verilog, and UVM.
- Experienced in debugging complex gate level simulations.
Work Experience
Intel Corporation
Senior SOC Pre-Si Verification Engineer (1 yr 9 mos)
Capgemini Engineering
Verification Engineer (3 yrs 5 mos)
Tessolve
Verification Engineer (2 yrs 6 mos)
Education
Bachelor of Technology - BTech at Chalapathi Institute of Engineering & Technology, Lam
