Amit Jain

CEO

Bengaluru, Karnataka, India20 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led a 20-member DV team at Qualcomm.
  • Spearheaded development of next-gen AI SoC.
  • Established DV flows from scratch at Nuvia.
Stackforce AI infers this person is a Semiconductor Design Verification Expert with extensive experience in SoC development.

Contact

amit.krjain84@gmail.comLinkedIn

Skills

Core Skills

Soc DesignDesign VerificationTeam LeadershipTestbench ArchitectureMemory Sub-system DesignVerification Ip DevelopmentProtocol VerificationRtl Design

Other Skills

SystemVerilogPerlVerilogASICUVMAMBA ProtocolsSoC architectureTechnical resolutionTeam managementTB architectureDV flowsEmulationTesting flowsDV flow developmentEnd-to-end DV

About

A seasoned Design Verification (DV) methodologist, Testbench architect, and SoC/Sub-system/IP DV lead with extensive experience across DV, design, and architecture roles at leading companies including Nuvia, Qualcomm, Ampere, and Mentor Graphics. Currently serving as Chip Lead for a next-generation AI accelerator SoC, I am driving the full-stack development from scratch—overseeing SoC architecture, design, and cross-functional technical resolution including floorplan and die-area convergence for this complex chip. In parallel, I am also leading and directly managing a 20-member DV team responsible for SoC DV activities across multimedia IPs in Qualcomm SoCs, including leadership for SoC DV of a cutting-edge automotive segment SoC. My career spans roles from individual contributor to project and team lead, with a proven track record in mentoring, team building, and scaling engineering teams from seed members to 50+ engineers.

Experience

20 yrs 6 mos
Total Experience
4 yrs 1 mo
Average Tenure
5 yrs 1 mo
Current Experience

Qualcomm

Principal / Manager

Mar 2021 – Present · 5 yrs 1 mo · Bengaluru, Karnataka, India

  • Chip Lead for AI Accelerator SoC: Spearheading end-to-end development of Qualcomm’s first next-gen AI SoC, enabling various cross functional teams with SoC development activities by helping to resolve dependencies and technical challenges.
  • In parallel, leading team of around 20 engineers, responsible for SOC DV of Multi-media IPs in all Qualcomm SOCs, driving next generation Automotive SOC. Team is responsible to drive planning, execution of the SOC DV from start till tape-out and even beyond that till CS.
SystemVerilogPerlVerilogASICRTL DesignUVM+3

Nuvia inc

SoC DV Engineer

May 2020 – Mar 2021 · 10 mos · Bengaluru, Karnataka, India

  • Seed member of Nuvia SOC DV team in Bangalore.
  • TB architect and methodologist - Helped developed multiple DV flows from scratch including Emulation, PSS, TB, Testing flows etc...
  • Led full end-to-end DFD/DFx DV from scratch till tape-out readiness for Nuvia data center SoC.
SystemVerilogTB architectureDV flowsEmulationTesting flowsDesign Verification+1

Ampere

Principal Engineer

Jun 2019 – Mar 2020 · 9 mos · Greater Bengaluru Area

  • Worked on memory sub-system DV.
  • Setup SDF based GLS from scratch for Memory sub-system, chaired internal GLS WG to setup right guidelines and process.
  • Defined DV strategy for memory sub-system for next gen chip.
  • Led team for ARM CHI coherency protocol in-house verification component development. Ramped up team on various protocol, TB architectural aspects.
Memory sub-system DVSDF based GLSARM CHI coherency protocolDesign VerificationMemory Sub-system Design

Mentor graphics

Senior Engineering Manager

Aug 2006 – May 2019 · 12 yrs 9 mos · Bengaluru, Karnataka, India

  • Seed member of Verification IP development team at Mentor.
  • Developed, deployed VIP products for medium to high complexity protocols across various domains such as USB2/3, AMBA (Including ARM coherency protocol), Display, Automotive and others such as I2C, OCP etc…
  • Led, managed teams doing VIP development, deployments.
  • Worked through different product phases, using VMs from AVM->OVM->UVM. Worked on trying out various architectures to make product portable across platforms beyond simulation.
VIP developmentProtocol deploymentUVMVerification IP DevelopmentProtocol Verification

Wipro technologies

Design Engineer

Jul 2005 – Aug 2006 · 1 yr 1 mo · Bangalore

  • Written RTL code for integer and floating point pipeline of VLIW processors which are part of a big design called physics processor.
RTL codingVLIW processorsRTL Design

Education

Indian Institute of Technology, Roorkee

B. Tech. — Electrical and Electronics

Jan 2001 – Jan 2005

Stackforce found 100+ more professionals with Soc Design & Design Verification

Explore similar profiles based on matching skills and experience

Navneet Goel

Navneet Goel

Senior Design Verification Engineer (L64)

at Microsoft

Delhi, India12 yrs 4 mos exp
Embedded SystemsLeadershipSoCSubsystem DebugSystem Verilog
AC

Abhishek Chopra

Manager

at AMD

Bengaluru, India22 yrs 4 mos exp
Project ManagementTeam LeadershipProgram ManagementDesign and VerificationDesign and Development
Sanjay Gupta

Sanjay Gupta

Chief Development Officer & India Country Head

at L&T Semiconductor Technologies

South Delhi, India28 yrs 9 mos exp
SemiconductorsEngineering ManagementR&DAutomotiveProduct Development
Mithun Srinivasan S

Mithun Srinivasan S

Design Verification Engineer

at MediaTek

Bengaluru, India2 yrs 9 mos exp
RTL VerificationVerification and Validation (V&V)
RC

R C.

IP/SubSystem/SoC Verification Engineer

at Microsoft

Portland, United States17 yrs 6 mos exp
Protocol KnowledgeVerification IP Development
Elizabeth Stratton

Elizabeth Stratton

Operations Lead

at Warwick Racing

Coleshill, United Kingdom3 yrs exp
LeadershipEvent PlanningSponsorship ManagementPublic SpeakingBusiness Operations
SP

Sravanthi Pedireddi

Technical Lead

at HCLTech

Bengaluru, India8 yrs 2 mos exp
SoC DesignASIC Design
Archana Krishnamurthy

Archana Krishnamurthy

Senior Technical Lead

at Intel Corporation

Bengaluru, India18 yrs 3 mos exp
Clock DistributionStatic Timing AnalysisTechnical LeadershipCircuit Design