Saroj Singh

Operations Associate

Bengaluru, Karnataka, India19 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

14+ years of experience in Mask Design and Physical Verifications.
Expertise in Memory Compiler Development and Analog Layout Design.
Hands-on experience with leading EDA tools and latest CMOS technologies.

Stackforce AI infers this person is a VLSI Design Engineer with extensive experience in semiconductor design and verification.

Contact

Skills

Core Skills

VlsiCircuit DesignMemory Layout DesignPhysical VerificationsFull Custom Memory LayoutAnalog Layout DesignAnalog Circuit Design

Other Skills

CadenceCMOSEDADRCLVSPEXDigital Layout DesignLayoutCadence VirtuosoASICIntegrated Circuit DesignSemiconductorsVHDL

About

 Posses 14+ yrs of Experience in Mask Design (Memory, Analog, Digital) and Physical Verifications. Memory Compiler Development and Layout: Pitched based Leaf Cell Level SRAM Layout and Compiler development. Analog Cell Layout: Matching of Devices i.e. common centroid, interleaving and proximity. Different types of shielding. Electro-migration and IR Issues solutions. Reliability Issues like Antenna, Latch-up and ESD In IO's   Hands on experience with leading EDA tools Cadence, Mentor Graphics Backend design and verification tools.  Worked on latest CMOS process technology from leading Fabs like; TSMC, IBM for technology nodes (180nm, 90nm, 45nm, 32nm, 28nm, 20nm).  Good fundamentals : Circuit Theory, Analog & Digital Layouts, CMOS Processing & Circuit Layout issues.  Knowledge of Hardware Language ( VHDL, Verilog ), C & Assembly language. Specialties: Memory Compiler and Analog Layout Design and Physical Verifications.

Experience

19 yrs 7 mos

Total Experience

3 yrs 4 mos

Average Tenure

12 yrs 8 mos

Current Experience

Synopsys india pvt ltd

2 roles

Manager

Promoted

Sep 2014 – Present · 11 yrs 7 mos

VLSICircuit DesignCadenceCMOSEDA

Sr Design Engineer

Jul 2013 – Aug 2014 · 1 yr 1 mo

Interra systems, bangalore

Sr. Design Engineer

Jul 2011 – Jul 2013 · 2 yrs · Bangalore

Working on Memory Full Custom Layout Design, top level integration and Physical Verifications.

Memory Layout DesignPhysical Verifications

Kpit cummins infosystems limited

MTS ( Member Of Technical Staff )

Mar 2010 – Mar 2011 · 1 yr · Bangalore, India

Full Custom Memory Layout cell development with all validations required for compiler delivery ( DRC/LVS/LFD/PEX ). Run Cut Level checks like MEMBEQA, MESH-ON-TOP, Pin Attribute, CDL Vs Verilog, Layout Vs Verilog, DRC, LFD, LVS

Full Custom Memory LayoutDRCLVSPEX