Pilli Sathavardhana Rao — Software Engineer

RF Design: 3D Modelling of components. Studied and worked on designing of inductor & capacitor (passive component design) using substrate integrated wave guides(SIW) technology in ANSYS HFSS . Design of component on substrate. SOS- system on substrate. S-parameter analysis and component device model extraction for the inductor & capacitor. Analog Circuit Design : Signal generator block design. Studied and worked on design of high performance Oscillator design using different models and at lower technologie nodes Colpitts capacitance divide model design of resonance tank using SIW components. Integrated system on chip(SOC) with system of substrate( SOS) and designed a high performance design that works from 1GHz to 300GHz range. Memory Design & Characterization : SRAM, DRAM & ROM. schematic design analysis of Bit cell, Sense amplifier, Local & Global control blocks. Study and analysis of bit cell in terms of Area, Power & Leakage, low voltage application & performance. Bit cell analysis to characterize Static Noise Margin(SNM), Read & Write margin, Leakage & Read current, Flip-time. Sense Amplifier offset analysis - Systematic offset & random offset analysis. Designed the memory block circuits in schematic and got netlist files and simulated using Eldo-simulator. worked on SRAM & ROM memory characterization. worked on memory timing analysis such as Address, Access, Setup, Hold, Cycle timing across PVT's. Writing measures and stimuli for the timing characterization. Good understanding of low power memory architectures such as multi banking architecture, divided word line architecture etc., Self timing path design and debugging of worst case & simulate across all PVT's. Analysis of liberty files across all the PVT's. Standard Cell Design & Characterization: Timing, Power, Noise & Variations. Standard cell design & characterization of basic logic gate cells like AND, OR, NAND, NOR, XOR, INV, BUF, FLOP etc..., Timing characterization using NLDM (non-linear delay) model, CCS(composite current source) model, ECSM( effective current source) model. Power characterization using NLPM(non -linear power) model CCSP model, ECSMP model. Noise characterization using CCSN model, NLDM model, ECSM model with CCC(channel connected components). Chip Variations using AOCV, POCV, SBOCV, LVF formats for liberty file . IO Characterization : DotLib & verilog view generation for timing, power & noise Working with lower node techologies with different IO models and physical view generation & Quality analysis.

Stackforce AI infers this person is a VLSI Engineer with expertise in Analog Circuit Design and Memory Characterization.

Location: Hyderabad, Telangana, India

Experience: 8 yrs 4 mos