shubham Maheshwari

Software Engineer

Bengaluru, Karnataka, India9 yrs 6 mos experience
Highly Stable

Key Highlights

  • Expert in RTL Design and Integration.
  • Proficient in Low Power Checks and Power Intent.
  • Strong experience in Automotive IP and SOC designs.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SOC development.

Contact

Skills

Core Skills

Rtl DesignRtl IntegrationPower Controller DesignDesign For Debug

Other Skills

Power IntentLow Power ChecksARM coresight IntegrationOTP controller DesignRTL QA ToolsVersion ControlAutomotive IP RTL DesignSOC Power Controller IP DesignsPower Controller IP DesignFuse Controller DesignSOC DebugSecurity Blocks DesignDebuggingProject ManagementProgramming

About

Currently working in QUALCOMM as staff Engineer with 9 years of experience .Below are expertise- logic design,RTL Integration power controller IP Designs Power Intent i.e. UPF/CPF development/Integration. Low Power Checks using Cadence CLP ARM coresight Integration OTP controller Design. RTL QA Tools such as Spyglass Linting,CDC etc. Ability to perform Complex ECOs Good knowledge of version control environment such as Clearcase

Experience

9 yrs 6 mos
Total Experience
9 yrs 6 mos
Average Tenure
9 yrs 6 mos
Current Experience

Qualcomm

6 roles

Staff Engineer

Dec 2023Present · 2 yrs 4 mos

RTL DesignRTL IntegrationPower IntentLow Power ChecksARM coresight IntegrationOTP controller Design+2

Lead Engineer, Sr

Dec 2021Dec 2023 · 2 yrs

  • working on Automotive IP RTL Design
Automotive IP RTL DesignRTL Design

Senior Hardware Design Engineer

Dec 2019Nov 2021 · 1 yr 11 mos

  • working on SOC power controller IP Designs
SOC Power Controller IP DesignsPower Controller Design

Engineer

Promoted

Dec 2017Nov 2019 · 1 yr 11 mos

  • worked on Power Controller IP Design for SOC.
  • Worked as Fuse controller Design Engineer for Premium Tier Qualcomm SOCs.
  • Worked as SOC Debug Lead for Premium 5G MODEM Chip
Power Controller IP DesignFuse Controller DesignSOC DebugPower Controller Design

Associate Engineer

Jul 2016Nov 2017 · 1 yr 4 mos

  • Worked on Design for Debug for complex SOC(Defining and Implementing system level Debug requirements using ARM coresight components).
  • Worked on security blocks design (Defining OTP contents and designing OTP controller).
Design for DebugSecurity Blocks Design

Interim Engineering Intern

May 2015Jul 2015 · 2 mos · Bangalore

  • Worked on Low Power Checks (CLP) over SOC RTL/Front End Netlist
Low Power Checks

Education

Motilal Nehru National Institute Of Technology

Bachelor of Technology (BTech) — Electronics and communication Engineering

Jan 2012Jan 2016

Board of Secondary Education Rajasthan

12th

May 2011Present

Board of Secondary Education Rajasthan

10th

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