Oct 2018 – Present · 7 yrs 7 mos · Bengaluru, Karnataka

• 1) Roles and Responsibilities:
• Performed a wide range of back-end activities, including Floorplan design, RTL synthesis, PnR, CTS, Timing closure (STA), DRC, Antenna checks
• Conducted multiple sessions for FTEs on optimized way of FP Design & use of RLS flow for partition convergence
• 2) Section Floorplan Owner:
• Planned high quality floorplan freeze of FTL sections with high pin density, FDI hips & macro placements
• Maintained higher utilization with 25Mn Gate counts of the most critical section in terms of wires exchanged to reduce area consumption
• Modified data flows to reduce pin density across interfaces to accommodate TSVs without compromising quality and chip specifications
• 3) Section Execution Owner:
• Led team of 5 to deliver 12 partitions with utmost quality of routing, timing and caliber convergence
• Generated scripts for custom routing and relaying of analog nets connecting different tiles
• 4) Partition Execution Owner:
• Converged varied complex partitions with high utilization (~70%), 4Mn Gate counts and 6K feedthroughs
• Used different techniques to place RPs and repeaters to minimize timing & routing convergence during ECO
• Executed Tweaker and different custom scripts to converge 65K min & 15K max violations across interfaces occurring due to high min-max skew differences
• 5) Section Timing Owner:
• Planned repeaters with respect to processes used for latency and RP depths reduction
• Generated partition related recipes with different relaying techniques to straighten and buffer feedthroughs to reduce routing and timing complexities