Ranjith Bidri — CEO

Digital ASIC verification engineer in verifying a complex low power processor architecture and VIP development. My areas of interest are in the advanced verification solutions and methodologies such as SystemVerilog, UVM, UPF, Assertion-Based Verification. Tools Used : - Synopsys : VCS, MVSIM, Verdi - Cadence : NCSIM - Mentor : Modelsim ,Questa Languages : - HDL : verilog ,VHDL - HVL: system verilog ,SVA - Methodlogy : Universal Verification Methodology (UVM) - software languages : C ,C++ Methodology : UVM Coverage : IMC Protocols : SPI, USB3.0, AHB , APB , AXI, OCP3.0 Specialties:System verilog & Besides Good Hands on Experience with System Verilog Assertions .

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in advanced verification methodologies.

Location: Bengaluru, Karnataka, India

Experience: 13 yrs 4 mos