Shashank Misra

Product Engineer

Noida, Uttar Pradesh, India16 yrs 1 mo experience
Highly Stable

Key Highlights

  • Expert in physical design and timing closure.
  • Proficient in Tcl scripting for electrical violations.
  • Experienced in leading engineering teams.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and verification.

Contact

LinkedIn

Skills

Other Skills

Timing ClosureASICPhysical DesignStatic Timing AnalysisPrimetimeTCLSoCVLSIPhysical VerificationApplication-Specific Integrated Circuits (ASIC)Very-Large-Scale Integration (VLSI)System on a Chip (SoC)

About

1-Handled different complexity level blocks from Floorplan stage and successfully tapeout GDS. 2- Handle multivolt rule checking using MVRC tool. 3- develop different script by using Tcl to handle different type of electrical violation of block. 4- Managed small team of engineers. Specialties: Floorplaning,placement,timing closure,physical verification

Experience

16 yrs 1 mo
Total Experience
2 yrs 10 mos
Average Tenure
1 yr 10 mos
Current Experience

Astera labs

Principal physical design Engineer

Jun 2024 – Present · 1 yr 10 mos · Toronto, Ontario, Canada · Hybrid

Qualcomm

Staff Design Engineer

Sep 2021 – Jun 2024 · 2 yrs 9 mos · Noida, Uttar Pradesh, India

Nxp semiconductors

2 roles

Design Engineer

Promoted

Oct 2017 – Oct 2021 · 4 yrs

  • PnR of Blocks
  • Flow development
  • Lead Activities

Engineer

Oct 2017 – Oct 2021 · 4 yrs

Broadcom

contractor

Jan 2015 – Jan 2016 · 1 yr

  • Block level sign-off closure

Amd

2 roles

Physical Design Engineer

Promoted

Jun 2010 – Dec 2012 · 2 yrs 6 mos

  • Doing Floorplan, placement and routing and working on full flow till tapeout of Graphic chip modules.

CAD Engineer

Sep 2009 – May 2010 · 8 mos

  • handling scripting part of tools to automate the Physical and route flow. I did Correlation between timing tools.

Vedant

design engineer

Feb 2004 – Jul 2007 · 3 yrs 5 mos

  • design engineer

Education

SRM University

M.Tech — VLSI

Jan 2007 – Jan 2009

Chhatrapati Shahu Ji Maharaj University

Master of Science (M.Sc.) — Electronics Science

Jan 1999 – Jan 2004

JP INTER COLLEGE

Intermediate — Science

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